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About the role

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. The company seeks a highly motivated and team-oriented individual to work with both layout and design engineers across multiple time zones. As an Integrated Circuit Designer - Layout, you will be part of a key team designing and developing sophisticated advanced node CMOS products.

Responsibilities

• Design and development of layout for integrated circuits according to electronics engineering principles, using software to create design schematics and diagrams, including floor planning, creating layouts of building blocks, and integrating layouts for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs in advanced CMOS nodes
• Focus on minimizing parasitic and skew, matching, EMIR, and antenna rules on top of DRC and LVS
• Management of manufacturing process of the products, including technology yield and performance of the products
• Development of test programmes and procedures to ensure the products meet their performance specifications
• Provision of advice on aspects of semiconductor process technology and maintain and repair semiconductor process equipment

Qualifications

• At least a bachelor’s degree in electrical engineering

Requirements

• 10+ years of experience in the development of layouts for high-speed analog IC designs in fin FET technology
• Experience with layout extraction tools and analyzing layout parasitic to achieve high quality layout for high-speed circuits
• EMIR and antenna DRC rules aware layout practices
• Experience writing SKILL and TCL scripts is highly recommended

Benefits

• Competitive salary
• 13th month salary
• Performance bonus each year
• Long Term Incentive (LTI)
• Health check each year
• Insurance for engineer and family
• Lunch Allowance
• Company trips