Jobs · OTHR · California

Template Job

Astera Labs · San Jose, CA · 1 wk ago
OTHR$207k–$230k/yrFull-time

Key Responsibilities

  • Analog & Mixed-Signal Design
  • Architect and design high-speed analog and mixed-signal circuits including PLLs, LDOs, references, high-speed SerDes building blocks, ADCs/DACs, and clocking.
  • Drive circuit design from specification and architecture through schematic, layout supervision, and verification across PVT corners.
  • Develop robust designs in advanced FinFET process nodes with attention to power, area, and performance trade-offs.
  • Silicon Execution & Validation
  • Lead silicon bring-up, characterization, and debug, partnering with validation and product engineering to root-cause and resolve issues.
  • Define and execute test plans to correlate silicon performance against design targets.
  • Technical Leadership
  • Set analog design methodology, review standards, and best practices across the team.
  • Partner cross-functionally with digital, physical design, systems, and architecture teams to deliver full-chip solutions.
  • Mentor and guide junior engineers, elevating the technical capability of the analog organization.

Basic Qualifications

  • MS or PhD in Electrical Engineering or a related field.
  • 8+ years of experience in analog and mixed-signal integrated circuit design.
  • Proven track record designing high-speed analog circuits such as PLLs, SerDes front-ends, data converters, references, or regulators in advanced CMOS/FinFET nodes.
  • Strong understanding of physical-layer design principles, signal integrity, and high-speed I/O.
  • Proficiency with industry-standard design and simulation tools (e.g., Cadence Virtuoso, Spectre) and solid layout/parasitic-aware design skills.

Preferred Qualifications

  • Experience taking multiple analog/mixed-signal designs through full production tape-out and high-volume manufacturing.
  • Expertise in high-speed serial link design (PCIe, Ethernet, UALink, UCIe) and associated PHY architectures.
  • Familiarity with silicon debug, ATE test development, and design-for-test techniques.
  • Experience mentoring engineers and leading technical design reviews.
  • Excellent communication skills and a collaborative, ownership-driven mindset.

Pay

Salary range is $207,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

Similar jobs

Template US jobs

NobiUnited States· 2 wk ago
RemoteOTHRapply on careers.nobi.life

Standard Job Template

Monster EnergyCorona, CA· 2 wk ago
OTHR$17–$22/hrapply on job-boards.greenhouse.io

Test Job Template

iCIMS Middleware Test CompanyAlabama, United States· 1 wk ago
Quality Assuranceapply on careers-test852.icims.com

Test Job Template

iCIMS Middleware Test CompanyMatawan, NJ· 5 mo ago
Consultingapply on external-notacustomer.icims.com