Technical Director, Packaging Engineering (AI2557)

About the role

SiMa.ai is looking for a Technical Director of Packaging Engineering to drive High Performance FCBGA and SiP packaging technology development to support SiMa.ai MLSoC™ IC roadmap from package definition and design through qualification to mass production. This is a hands-on technical leadership role with personal ownership of package design and SI/PI for high-speed LPDDR and PCIe interfaces. The candidate will be responsible for packaging strategy and OSAT/substrate supplier relationships, directing, and coordinating all packaging activities to develop the package and ramp it up to high-volume production, ensuring world-class product quality, capacity and best possible cost.

Responsibilities

• Own package SI/PI hands-on for high-speed interfaces — LPDDR5x/6 DRAM and PCIe Gen5, plus 10G Ethernet and MIPI: chip–package–board co-design, channel and PDN simulation (loss, crosstalk, eye margin, PDN impedance, IR drop), and lab correlation
• Lead and coordinate advanced package development activities from package definition (architecture, bump/ball map, substrate stack-up, body size) and design to mass production, including all aspects of high density/high performance interconnects design, thermo-mechanical (warpage, lid/stiffener, thermal), quality, reliability, cost, and yield constraints
• Definition and implementation of FCBGA and SiP packaging strategies for high-speed complex mixed-signal ICs in close collaboration with Design, Hardware, and Quality teams
• Drive OSAT and substrate supplier relationships: selection, technical and commercial negotiation, capacity, process and material qualification, PCN review, and yield/cost roadmaps
• Packaging NPI activities including characterization, qualification (JEDEC, AEC-Q100, board-level reliability) and productization at the right cost and quality for tier-1 customers, including Automotive Package production control, issues resolution, yield/DPPM monitoring and improvement
• Support package RMA and FA activities, working closely with QA and Design teams
• Representing Packaging Engineering to SiMa.ai customers
• Build and lead a compact package design and SI/PI team as a player-coach, personally reviewing layouts and simulation results

Requirements

• BS/MS in Electrical Engineering, Mechanical Engineering, Material Science or a related field with 10+ years relevant experience in FCBGA/SiP package design and development
• Hands-on SI/PI design and simulation of high-speed DRAM (LPDDR5x/6), PCIe (Gen5), UCIe channels and PDN at package and board level, using tools such as Ansys HFSS/SIwave, Cadence Sigrity/Clarity, or Keysight ADS, with lab correlation (VNA/TDR, eye measurements)
• Hands-on package substrate design: bump/ball map, stack-up, routing, and design-rule trade-offs with substrate vendors (Cadence APD+/SiP Layout or equivalent)
• SiP experience: multi-die and SoC-plus-memory integration, passive integration, and the related assembly and test challenges
• Proven track record driving OSATs and substrate suppliers from package definition through