Staff VLSI Design Engineer

About the Role

The Memory Technology Group is at the core of Sandisk's engineering organization. We are building a cutting edge 3D memory in our multi-billion dollars lab. The Memory Technology organization functions as a start-up within Sandisk, offering a creative, fast paced, entrepreneurial work environment at the center of innovation. We are looking for an experienced Staff Engineer to lead and deliver projects for our Memory Design team. This is a great opportunity for a results-oriented, entrepreneurial individual who knows how to work with non-volatile memory world-class engineers and has a great track record for delivering innovative results. You will need to think creatively about the memory as we do take pride in our craftsmanship. Your success will be measured by your ability to build great designs that deliver innovation that unlock revenue opportunities for the company.

Responsibilities

• RTL design and verification in Verilog, RTL linting, clock domain crossing (CDC) analysis, design integration, synthesis, DFT, timing analysis and closure
• Balance design trade-offs with modularity, scalability, power, area, and performance
• Interface with internal and external teams/customers to drive necessary technical specifications and features based on individual requirements
• Participate in Post-Si evaluation and debug
• Drive cross function support for productization
• Provide technical guidance and mentoring of junior engineers

Qualifications

• Master of Science in Electrical Engineering or related field, plus 6-8 years of relevant experience
• Experience with chip level integration, chip lead, and full product life cycle (requirements, design, implementation, test) of Logic design
• Working knowledge of the entire Logic design flow from RTL to GDSII (RTL coding, simulation, synthesis, static timing analysis, logic equivalence, DFT insertion, place-and-route, clock tree synthesis, extraction, static timing analysis, physical verification)
• Working knowledge of NAND flash memory cell device operations, algorithms for program/read/erase
• Excellent communication (written and verbal) and interpersonal skills

Preferred Skills

• Experience developing digital circuit designs for low power operating conditions
• Working knowledge of device physics and process
• Working knowledge of NAND Flash memory design including Analog, Core, Datapath and IO circuits
• Proficiency with following Digital design tools: Synthesis - Synopsys Design Compiler, Cadence Genus or Cadence RTL Compiler; Static Timing - Synopsys Primetime or Cadence Tempus; Place and Route - Synopsys ICC or Cadence Encounter or Innovus
• Familiarity with revision control tool and EDA standard formats used in cell/library development and modeling - Liberty (timing model), SDC (Synopsys Design Constraints)
• Programming experience in C, C++, Python or Perl