Staff Engineer, RTL Implementation
About the Role
Join our CPU design team to iterate through front-end CAD flows on multiple process technologies while working closely with core micro-architects to refine CPU core configurations and optimize PPA. You’ll work on a CPU based on RISC-V ISA, collaborating with DV, PD, RTL, and performance teams to deliver a functional, timing, and power-converged design. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels.
Responsibilities
- Perform synthesis and initial place and route for new and legacy designs.
- Collaborate closely with core micro-architects to optimize core configurations for best PPA.
- Use innovative techniques to optimize power, performance, and area while driving physical design experiments and evaluating results.
- Enhance physical design environment, tools, and methodologies to improve development efficiency.
Requirements
- Experienced in high-performance physical design.
- Proficient in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation and power analysis.
- Skilled in synthesis, place and route tools including flows and physical design methodology.
- Background in CPU micro-architecture.
What You Will Learn
- End-to-end exposure to CPU design from microarchitecture through timing and power convergence.
- Hands-on experience optimizing CPU designs and driving PPA improvement.
- Integration of open-source and industry-standard tools to improve physical flows and results.
- Work in a deeply technical, highly collaborative team solving cutting-edge CPU design challenges.
Pay
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background, and location all impact the actual offer made.
Tenstorrent offers a highly competitive compensation package and benefits. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology.