Jobs · Engineering · California

Staff Engineer, PCIe PHY/Link Analysis

Samsung Semiconductor · San Jose, CA · 6 days ago
Engineering$163k–$253k/yrFull-time

Advancing the world’s technology together, our solutions power the tools you use every day—including smartphones, electric vehicles, hyperscale data centers, IoT devices, and more. Here, you’ll have the opportunity to be part of a global leader whose innovative designs push the boundaries of what’s possible and shape the future. We believe innovation and growth thrive in an inclusive culture with a diverse workforce, empowering people to be their true selves while building a better tomorrow for employees, customers, partners, and communities.

About the role

At the Technology Enabling Development Lab (TED), our core focus is the host interface firmware layer that bridges system software and flash management firmware. This key technology drives Samsung’s breakthrough V-NAND and enables enterprise-class applications such as hyperscale data centers, big data processing, and software-defined virtualized storage. We are seeking a dynamic, self-motivated engineer to develop and support our cutting-edge Enterprise and Data Center SSD products. This position is based in San Jose, California and requires up to 25% business travel.

Responsibilities

  • Protocol Stack Analysis: Understand PHY/Link architecture, implementation, and integration of the PCIe protocol stack from the Physical Layer through the Data Link Layer to the Transaction/Transport Layer, collaborating with internal hardware teams and external vendors.
  • Link Bring-up & Training: Own LTSSM behavior, link training and equalization sequencing, PCIe enumeration, and configuration-space flows during device bring-up.
  • Transaction/Transport Layer: Analyze and validate TLP/DLLP handling, flow control, credit management, ordering rules, ACK/NAK and replay, error handling (AER), and end-to-end data integrity across the stack.
  • Debug & Optimization: Analyze and debug complex PHY, Link, and Transport layer issues during bring-up and sustaining stages of NVMe SSD products, from Gen1 to the latest generation (Gen7), covering protocol (LTSSM / PCIe enumeration) and PCIe feature-related issues.
  • Compliance & Standards: Participate in and support industry PHY/Link compliance tests, including PCI-SIG events.
  • Field Support: Provide onsite support for PHY/Link related tasks at customer sites and labs.

Requirements

  • BS in Computer/Electrical/Electronic Engineering or Computer Science with 8+ years of relevant experience in hardware, or an MS in the same fields with 5+ years of relevant experience.
  • Deep proficiency with the PCIe protocol spanning the Physical Layer through the Data Link Layer to the Transaction/Transport Layer.
  • Strong hands-on knowledge of LTSSM, link training/equalization, PCIe enumeration, flow control, replay/retry, and error handling (AER).
  • Working knowledge of PHY-layer operation (CDR to Equalizer such as VGA, CTLE, DFE, FFE, DSP, etc.) to root-cause link issues crossing the PHY/Link boundary.
  • Solid experience in C/C++ for embedded systems, and expertise with UART/JTAG/ICE debuggers and general firmware debugging techniques.
  • Strong experience with PCIe protocol analyzers, logic analyzers, and signal analyzers for link and transaction-level debug.
  • Ability to work effectively within a multi-functional team environment.

Preferred Skills

  • Knowledge of signal integrity/power integrity (SI/PI) for PCIe.
  • Proficiency in NVMe, CXL, or SAS/SATA protocols.
  • Experience in pre-silicon and post-silicon SoC validation.
  • Experience with PCIe power management (ASPM, L1 substates) and low-power link states.

Benefits

  • Medical, dental, vision, and 401k plans.
  • Charitable giving match and community involvement opportunities.
  • 4+ weeks of paid time off annually, plus holidays and sick leave.
  • Family care support, including fertility/adoption stipends, medical travel support, and virtual vet care.
  • On-demand emotional wellness apps and free confidential therapy sessions.
  • Onsite café and gym, plus virtual fitness classes.
  • Flexible work environment.

Pay

Base pay range: $163,000—$253,000 USD. Incentive opportunities reward employees based on individual and company performance.

Similar jobs

Staff Engineer I - P2P

Western Alliance BankPhoenix, AZ· 3 wk ago
Engineeringapply on westernalliancebank.wd5.myworkdayjobs.com