Staff Engineer, Architecture & Performance Research Engineer for Data Center and Agentic AI CPU

About the role

The Architecture Research Lab focuses on researching next-generation CPU (RISC-V) microarchitecture and performance for emerging computing workloads. We explore new architectural ideas, evaluate their performance potential, and rapidly turn promising concepts into working designs that can be validated on real silicon. Our research is driven by emerging opportunities in data center and agentic AI workloads, where we investigate how CPU architecture can evolve to meet new performance and efficiency requirements. We also explore CPU-memory co-design from the CPU perspective, in alignment with the broader shift toward memory-centric architectures.

Responsibilities

• Identify opportunities across emerging workloads
• Develop and refine performance models
• Evaluate system-level architectural trade-offs
• Drive new microarchitectural concepts from research to implementation
• Work closely with RTL design teams to translate architectural concepts into implementable designs
• Guide key technical decisions
• Validate the impact of architectural concepts from modeling through silicon
• Shape the architecture and performance direction of next-generation CPU architectures
• Propose new architecture ideas and take ownership of one or more microarchitectural domains
• Use AI-driven design methodologies to rapidly implement architectural ideas and validate them on real silicon
• Build, extend, and validate performance models and architectural simulators
• Perform CPI/IPC analysis and identify root causes of performance bottlenecks
• Evaluate microarchitectural features and optimizations using trace-driven, analytical, and cycle-accurate models
• Characterize workloads and benchmarks, including SPEC, server, client, AI/ML, agentic AI, and internal traces
• Translate performance analysis and modeling results into architectural direction and design decisions
• Drive research leading to patents and technical publications

Requirements

• Master’s degree in Computer Engineering, Computer Science, or a related field with 8+ years of relevant experience, or PhD with 5+ years of relevant experience
• 4+ years of experience in CPU microarchitecture or performance engineering
• Experience designing RISC-V, ARM, x86 CPU cores, or GPU/NPU vector unit
• Strong understanding of out-of-order execution, branch prediction, pipelines, speculation, and cache/memory systems
• Hands-on experience with architectural simulators such as gem5
• Proficiency in C/C++ and Python
• Experience analyzing large-scale performance data and traces

Qualifications

• Experience with AI-driven or agentic design workflows, including high-level design languages and AI-assisted RTL generation, or a strong interest in and ability to quickly learn such methods
• Domain-specific experience in one or more of the following areas: Front-end: Branch prediction and decoupled fetch, particularly for compiler- or interpreter-driven workloads Mid-end: RVV/SIMD, matrix/tensor engine design, and out-of-order vector execution Back-end: LSU/MSHR design and prefetcher design for irregular access patterns
• Experience with PPA trade-off analysis
• Experience leading and mentoring junior engineers
• Experience with CPU tapeout or silicon validation
• Experience with patents or technical publications

Skills

• Master’s degree in Computer Engineering, Computer Science, or a related field with 8+ years of relevant experience, or PhD with 5+ years of relevant experience
• 4+ years of experience in CPU microarchitecture or performance engineering
• Experience designing RISC-V, ARM, x86 CPU cores, or GPU/NPU vector unit
• Strong understanding of out-of-order execution, branch prediction, pipelines, speculation, and cache/memory systems
• Hands-on experience with architectural simulators such as gem5
• Proficiency in C/C++ and Python
• Experience analyzing large-scale performance data and traces
• Experience with AI-driven or agentic design workflows, including high-level design languages and AI-assisted RTL generation, or a strong interest in and ability to quickly learn such methods
• Domain-specific experience in one or more of the following areas: Front-end: Branch prediction and decoupled fetch, particularly for compiler- or interpreter-driven workloads Mid-end: RVV/SIMD, matrix/tensor engine design, and out-of-order vector execution Back-end: LSU/MSHR design and prefetcher design for irregular access patterns
• Experience with PPA trade-off analysis
• Experience leading and mentoring junior engineers
• Experience with CPU tapeout or silicon validation
• Experience with patents or technical publications

Benefits

• Base Pay Range: $163,000—$253,000 USD

Pay

$163,000—$253,000 USD

Schedule

Daily onsite presence at our San Jose office in alignment with our Flexible Work policy

Qualifications

• Master’s degree in Computer Engineering, Computer Science, or a related field with 8+ years of relevant experience, or PhD with 5+ years of relevant experience
• 4+ years of experience in CPU microarchitecture or performance engineering
• Experience designing RISC-V, ARM, x86 CPU cores, or GPU/NPU vector unit
• Strong understanding of out-of-order execution, branch prediction, pipelines, speculation, and cache/memory systems
• Hands-on experience with architectural simulators such as gem5
• Proficiency in C/C++ and Python
• Experience analyzing large-scale performance data and traces
• Experience with AI-driven or agentic design workflows, including high-level design languages and AI-assisted RTL generation, or a strong interest in and ability to quickly learn such methods
• Domain-specific experience in one or more of the following areas: Front-end: Branch prediction and decoupled fetch, particularly for compiler- or interpreter-driven workloads Mid-end: RVV/SIMD, matrix/tensor engine design, and out-of-order vector execution Back-end: LSU/MSHR design and prefetcher design for irregular access patterns
• Experience with PPA trade-off analysis
• Experience leading and mentoring junior engineers
• Experience with CPU tapeout or silicon validation
• Experience with patents or technical publications

Skills

• Master’s degree in Computer Engineering, Computer Science, or a related field with 8+ years of relevant experience, or PhD with 5+ years of relevant experience
• 4+ years of experience in CPU microarchitecture or performance engineering
• Experience designing RISC-V, ARM, x86 CPU cores, or GPU/NPU vector unit
• Strong understanding of out-of-order execution, branch prediction, pipelines, speculation, and cache/memory systems
• Hands-on experience with architectural simulators such as gem5
• Proficiency in C/C++ and Python
• Experience analyzing large-scale performance data and traces
• Experience with AI-driven or agentic design workflows, including high-level design languages and AI-assisted RTL generation, or a strong interest in and ability to quickly learn such methods
• Domain-specific experience in one or more of the following areas: Front-end: Branch prediction and decoupled fetch, particularly for compiler- or interpreter-driven workloads Mid-end: RVV/SIMD, matrix/tensor engine design, and out-of-order vector execution Back-end: LSU/MSHR design and prefetcher design for irregular access patterns
• Experience with PPA trade-off analysis
• Experience leading and mentoring junior engineers
• Experience with CPU tapeout or silicon validation
• Experience with patents or technical publications