Principal Engineer, Architecture & Performance Research Engineer for Data Center and Agentic AI CPU

About the role

The Principal CPU Architecture & Performance Engineer will define the architectural vision and performance direction for next-generation CPU platforms. They will identify opportunities across emerging workloads, shape long-term architectural strategies, develop and refine performance models, and drive new microarchitectural concepts across multiple architectural domains.

Responsibilities

• Define the application-specialization direction for next-generation CPU cores, including agentic AI and memory-centric architectures, and lead the overall microarchitectural vision
• Lead end-to-end performance analysis using architectural simulators and RTL, guiding key architectural trade-offs and decisions
• Translate workload characterization and performance insights into architectural requirements and long-term design direction
• Work closely with RTL design teams and cross-functional engineering partners to translate architectural vision into implementable designs, influence key technical decisions, and validate architectural choices from modeling through silicon
• Drive architecture-to-implementation alignment with design teams, ensuring architectural intent is carried through RTL and silicon
• Mentor Senior and Staff engineers and provide technical leadership across multiple projects and architectural domains
• Drive research and technical contributions leading to patents and publications

Requirements

Master’s degree in Computer Engineering, Computer Science, or a related field with 18+ years of relevant experience, or PhD with 15+ years of relevant experience. Extensive experience designing and evaluating high-performance CPU architectures, including RISC-V, ARM, or x86 cores; experience with GPU/NPU vector or accelerator architectures is also relevant. Proven ability to use quantitative performance analysis and modeling to identify architectural opportunities, evaluate system-level trade-offs, and influence major microarchitectural decisions. Deep expertise in at least one major microarchitectural domain, with the ability to drive architectural direction and technical decisions in that area.

Qualifications

• Experience defining or influencing CPU architecture for emerging workloads, particularly AI/ML, agentic AI, or data center applications
• Experience with AI-driven architecture and design methodologies, including AI-assisted architecture exploration, high-level design, or RTL generation
• Experience with memory-centric architectures and CPU-memory co-design, with experience translating memory-system characteristics into CPU architectural opportunities
• Experience driving system-level PPA trade-offs across performance, power, area, and implementation complexity
• Experience taking architectural concepts through RTL implementation, tape-out, and silicon validation
• Experience leading cross-functional architecture initiatives and influencing technical direction across multiple engineering teams
• Proven ability to mentor and develop senior technical engineers and shape architecture research across multiple domains

Skills

Strong programming skills in C/C++ and Python, with experience developing tools and automation for performance analysis and architectural exploration. Demonstrated ability to take architectural concepts from research and modeling through RTL implementation and silicon validation.

Benefits

Base Pay Range: $219,000—$351,000 USD

Pay

TBD

Schedule

Daily onsite presence at our San Jose office in alignment with our Flexible Work policy