Staff DFT Engineer

About the Role

Arm’s Solutions group DFT team implements DFT for SOC across client, datacenter, automotive, and IoT lines of business using the latest DFT and process technologies. We collaborate closely with Arm’s partners and internal RTL, Verification, Physical Implementation, and Test engineering teams throughout the project lifecycle—from early investigation through tape-out and silicon test/characterization on ATE. Positions are available in San Jose and Austin.

Responsibilities

• Architect, implement, and validate innovative DFT techniques on SOCs and sub-systems.
• Insert DFT logic at SoC and sub-system levels and validate all DFT features using industry-standard simulation tools.
• Run RTL, unit delay, and timing-annotated gate-level simulations.
• Generate ATPG patterns and debug coverage issues to meet targets.
• Develop and validate design-for-test timing requirements, review timing reports, and provide fixes.
• Collaborate with multi-functional teams to support DFT RTL insertion, synthesis, scan insertion, place-and-route, static timing analysis, and timing closure.
• Participate in ATE-targeted test pattern validation and silicon debug.
• Collaborate with Test and Product Engineering teams on silicon characterization and validation.

Requirements

• Bachelor’s or Master’s degree in Electronic Engineering, Computer Engineering, or a related field.
• 10+ years of experience in Design for Test (DFT) as a Staff DFT Engineer.
• Core DFT skills, including experience with some of the following:
  • Siemens DFT tools
  • Streaming Scan Network (SSN)
  • Scan compression and insertion
  • Memory BIST and repair scheme implementation
  • Logic BIST
  • JTAG/IJTAG
  • At-speed test, ATPG, fault simulation
  • Back-annotated gate-level verification
  • Silicon debug, memory and scan diagnostics
• Experience coding Verilog RTL, TCL, and/or Perl.
• Experience with Cadence and/or Synopsys DFT and simulation tools.

Nice-to-Have Skills

• Familiarity with SoC-style architectures, including multi-clock domains and low-power build practices.
• Experience with Arm IP such as Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink interconnects, and CoreSight debug.
• Background in high-performance build, implementation, and DFT timing constraints.
• Experience with datacenter chips.
• Experience with 2.5D and 3D test.
• Ability to work collaboratively on a team and independently.
• Innovative mindset with a passion for progress.
• Strong time management skills and ability to multitask.
• Positive approach to working on cutting-edge projects.
• Excellent communication skills across global teams and time zones.

Pay

Salary range: $198,100–$268,000 per year. Salary is one component of Arm’s total reward package, which will be shared during the recruitment process.

Schedule

Arm’s hybrid working approach empowers teams to determine their own hybrid working patterns based on the work and team needs. Details will be shared upon application.

Benefits

• Accommodations available during the recruitment process (e.g., breaks between interviews, document accessibility, office accessibility). Requests are treated confidentially.