SRAM Layout Design Engineer

About the role

A senior-level SRAM layout design engineer with extensive experience in advanced CMOS technology nodes. This role involves full ownership of the custom layout process for SRAM memory components, including bitcell arrays, peripheries, test structures, and memory macros. The position offers the opportunity to work on cutting-edge process nodes in a collaborative environment, contributing to high-quality memory IP development.

Responsibilities

• Manage the complete custom layout process for SRAM bitcell arrays, peripheries, test structures, and memory macros utilizing advanced CMOS technologies.
• Develop and optimize floorplans for memory arrays, including placement, power grid design, routing channels, and macro assembly.
• Perform, debug, and complete design rule checks (DRC), layout versus schematic (LVS), electrical rule checks (ERC), antenna checks, and other physical verification tasks with tools such as Calibre and ICV.
• Support parasitic extraction, electromigration (EM) and IR drop analysis, power integrity, density/fill considerations, DFM, dummy insertion, and layout-dependent effects to ensure successful tapeout.
• Collaborate with circuit designers to translate schematics into layouts, prioritizing matching, symmetry, shielding, parasitic control, and reliability constraints.
• Work with front-end design, PnR, and integration teams to resolve top-level layout issues, pin accessibility, routing, power delivery, and macro integration.
• Develop and refine layout methodologies, checklists, and best practices to ensure consistent delivery of high-quality memory IP.
• Partner with foundry, CAD, and methodology teams to interpret design rules, process constraints, waivers, and rule deck behavior for advanced nodes.
• Review layouts, mentor junior engineers, and contribute to raising layout quality and process rigor across the team.

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent technical field.
• Over 10 years of hands-on IC layout experience, with at least 5 years dedicated to SRAM, memory compiler, or full-custom memory IP layout.
• Proven experience directly executing custom digital SRAM layouts, rather than solely reviewing or overseeing layouts.
• Extensive experience with advanced process nodes at TSMC 3nm or more advanced – experience with 10nm or 7nm is insufficient; 5nm is a plus.
• Strong understanding of SRAM and memory layout principles, including layout-dependent phenomena such as LOD, density, fill, masking, matching, and electromigration.
• Proficiency in Cadence Virtuoso for custom layout creation and assessment.
• Skilled in DRC/LVS debugging using tools like Calibre and ICV.
• Deep knowledge of floorplanning, block-level routing, macro assembly, pin planning, and top-level physical verification.
• Familiarity with advanced-node layout limitations, including layout-dependent effects such as IR drop and layout-dependent variability.
• Ability to collaborate effectively with circuit teams, PnR teams, foundries, and CAD teams.
• Strong communication skills, ownership, judgment, and mentorship capabilities.

Pay

$73.50 – $77.00 hourly

Schedule

This position is based in office and requires employee to work on-site.