Senior SRAM Layout Design Engineer
About the role
NVIDIA is seeking a Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. This is a senior individual contributor role for someone who can produce complex layouts, make informed advanced-node tradeoffs, improve layout methodology, and guide junior engineers.
Responsibilities
- Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies.
- Develop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly.
- Carry out, debug, and complete DRC, LVS, ERC, antenna, and associated physical verification checks with tools such as Calibre, ICV, or similar workflows.
- Support EM/IR review, power integrity, density/fill, DFM, dummy insertion, layout-dependent effects, and other requirements for tapeout.
- Collaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints are maintained.
- Collaborate with PnR and integration teams to resolve top-level DRC/LVS, pin access, boundary, routing, power-grid, and macro-integration issues.
- Implement and advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery.
- Collaborate with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and advanced-node process constraints.
- Review layouts, mentor junior engineers, and help raise layout quality and execution rigor across the team.
Requirements
- Have a BSEE or equivalent experience
- 10+ years of custom IC layout experience, including 5+ years in SRAM, memory compiler, or full-custom memory IP layout
- Hands-on participation in advanced CMOS technology initiatives, preferably concentrating on FinFET or GAA nodes at 5nm, 3nm, or smaller dimensions
- Solid grasp of SRAM and memory layout principles
- Extensive experience in Cadence Virtuoso applied to custom layout creation and assessment
- Extensive experience in DRC/LVS debugging using Calibre, ICV, or similar physical verification tools
- Experience with floorplanning, block-level routing, macro assembly, pin planning, boundary/interface management, and top-level physical verification
- Direct familiarity with advanced-node layout limitations and layout-dependent phenomena, including LOD, density/fill, matching, symmetry, shielding, electromigration, IR drop, and DFM or similar expertise
- Ability to work effectively with circuit build, physical build, integration, CAD, and foundry teams
- Clear communication, strong ownership, good judgment, and the ability to mentor other engineers
Qualifications
- Experience in scripting using Cadence SKILL, Python, or comparable languages for layout automation, checks, reporting, or improving workflows
- Strong familiarity with EM/IR, reliability, density, fill, DFM, and post-processing closure at both IP and top level
Skills
- Advanced CMOS technology experience
- Custom IC layout experience
- SRAM and memory layout principles
- Cadence Virtuoso proficiency
- DRC/LVS debugging skills
- Floorplanning and block-level routing experience
- EM/IR, reliability, density, fill, DFM expertise
Benefits
- Comprehensive benefits package
- Competitive salaries based on location, experience, and position level
- Equity options
Pay
Base salary range: $132,000 - $207,000 for Level 4, and $148,000 - $235,750 for Level 5.
Schedule
Full-time
Company Information
As one of the technology world's most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.