SRAM Compiler Engineer, AI Hardware

The Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. The team designs and develops advanced AI inference chips tailored to accelerate Tesla’s machine learning capabilities. Key projects include Dojo, a custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. This work powers the neural networks behind Full Self-Driving (FSD) and Tesla’s humanoid robot, Optimus.

Responsibilities

• Compile and validate SRAM macros across depth, width, port, and mux configurations using industry memory compilers
• Partner with architecture teams to define banking strategies—evaluate tradeoffs between number of banks, port configurations, and access patterns to hit PPA targets
• Optimize SRAM configurations for maximum bit-cell density and access speed—drive aspect ratio, redundancy, and compiler option choices
• Analyze and minimize SRAM read and write power—characterize active, leakage, and retention power across PVT corners
• Own delivery of all SRAM physical and logical views—GDS, LEF, Liberty timing models, and abstracts—validated for implementation and signoff
• Build and maintain automated SRAM compilation flows using agentic AI to generate, configure, and validate memory macros across design variants
• Support RTL teams on SRAM hook-up—review wrapper RTL, validate interface timing, and resolve connectivity and protocol issues
• Drive SRAM BIST and redundancy integration—validate repair schemes and yield enhancement strategies
• Characterize SRAM timing across MMMC corners and validate against STA signoff requirements
• Evaluate new compiler releases and bit-cell options at advanced nodes—benchmark PPA against current baselines

Requirements

• Degree in Electrical Engineering, Computer Engineering, or related field, or equivalent work experience
• 5+ years of SRAM compiler and memory design experience on high-performance SoCs
• Deep expertise in SRAM banking, configuration, and PPA optimization
• Strong understanding of SRAM read/write power, leakage, and retention characteristics
• Experience delivering complete SRAM macro views for physical implementation and signoff
• Ability to use agentic AI flows to automate SRAM compilation, configuration sweeps, and validation

Qualifications

• Hands-on experience with industry memory compilers (ARM, Synopsys, Cadence, or equivalent)
• Ability to use agentic AI flows to automate SRAM compilation, configuration sweeps, and validation

Skills

• Knowledge of SRAM banking, configuration, and PPA optimization
• Experience with industry memory compilers (ARM, Synopsys, Cadence, or equivalent)
• Understanding of SRAM read/write power, leakage, and retention characteristics
• Experience delivering complete SRAM macro views for physical implementation and signoff
• Ability to use agentic AI flows to automate SRAM compilation, configuration sweeps, and validation

Benefits

• Competitive pay
• Medical plans
• Dental (including orthodontic coverage) and vision plans
• Company Paid (Health Savings Accounts) HSA Contribution
• Flexible Spending Accounts (FSA)
• 401(k) with employer match
• Employee Stock Purchase Plans
• Other financial benefits
• Basic Life, AD&D Short-term and long-term disability insurance
• Employee Assistance Program
• Sick and Vacation time
• Paid Holidays
• Back-up childcare and parenting support resources
• Voluntary benefits to include: critical illness, hospital indemnity, accident insurance, theft & legal services, and pet insurance
• Weight Loss and Tobacco Cessation Programs
• Tesla Babies program
• Commuter benefits
• Employee discounts and perks program