SRAM Circuit Design Intern, MS - Summer 2027

About the role

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell's Central Engineering Foundational IP team is looking for a motivated SRAM Circuit Design Intern to join us in Burlington, VT. You'll work hands-on as part of a team designing, verifying, and characterizing high-performance memory used in cutting-edge semiconductor technologies. This role is an incredible opportunity to apply your digital and analog circuit design fundamentals while collaborating with experienced engineers on real-world products that are deployed at scale. Are you ready to use your engineering background to innovate and deliver the data infrastructure technology that connects the world and enables the powerful AI tools that are revolutionizing our industry? The Central Engineering Memory Development team designs and implements cutting edge memory solutions for state-of-the-art ASICs and business units within Marvell. As a member of the Memory Development team you will join a select group of engineers working in the world’s most advanced process technologies and forge the way for industry leading chip design. The team designs custom SRAM compilers, hardware security IP, and software to guide System on Chip (SoC) memory usage in advanced Gate All Around (GAA) and FinFET semiconductor nodes. This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates.

Responsibilities

• Design and implement custom digital circuits optimizing Power, Performance, and Area metrics (PPA)
• Schematic entry (Cadence Virtuoso)
• Circuit Simulation (Spectre, MDL)
• Verification (Verilog, VHDL)
• Statistical analysis of complex circuits across a wide Process, Voltage and Temperature range
• Process and visualize data using scripting tools (Perl, Python, Copilot)
• Verilog test pattern generation, simulation and waveform debug for large, complex memory designs
• Analyze, summarize, document, and present results to stakeholders to justify design approaches

Requirements

Currently pursuing a Master’s Degree in Electrical Engineering or a related field with an expected graduation date between Fall 2027 – Summer 2028.

Qualifications

• Familiarity working in a Unix/Linux environment
• Understanding of analog or digital memory circuits
• Strong Programming Skills in common scripting languages
• Previous exposure to Cadence design tools
• Ability to work independently with regular check-ins and team support
• Strong verbal and written communication skills

Benefits

• Medical, dental, and vision coverage
• Perks and discounts
• Robust mental health resources to prioritize emotional well-being