Jobs · Art & Creative · New York

Digital IC Design Intern, MS - Summer 2027

Marvell Technology · Hudson, NY · 3 wk ago
Art & CreativeInternship

About the role

Marvell’s Digital IC (or Digital Logic) Design teams span multiple domains, working on technologies that power next‑generation cloud, AI, storage, and networking solutions. Some teams design and verify high‑performance Ethernet PHY chips; others shape the micro‑architecture of blocks, accelerators, and subsystems that make up a system‑on‑chip (SoC). You will collaborate with your direct team and cross‑functional partners (architecture, physical design, design verification, etc.) to deliver robust, scalable solutions that enable Marvell’s leadership in data infrastructure.

Responsibilities

  • Deep dive into the digital design and implementation of real chip design efforts
  • Develop and verify detailed, high‑performance RTL design blocks and apply digital design specifications for high‑speed connectivity devices and next‑generation chips
  • Conduct synthesis, static timing analysis, timing signoff, and power analysis
  • Debug design issues and ensure functional correctness
  • Investigate and execute new design techniques and flows, and explore emerging methodologies to improve design quality, efficiency, and productivity
  • Collaborate with chip architecture, design verification, and physical design teams to solve complex problems and contribute to a team building real products

Requirements

  • Currently enrolled in a Master’s Degree in Electrical Engineering, Computer Engineering, or a related field with an expected graduation date between Fall 2027 – Summer 2028
  • Completed courses focusing on circuit design, circuit theory, digital logic design, static timing analysis, computer architecture, Verilog, VLSI, digital signal processing (DSP), SoC/ASIC design, or electronics
  • Proficiency in programming & scripting languages such as Python, Perl, Tcl
  • Experience using tools like Synopsys (Primetime), Cadence (Virtuoso & Spectre X), and Mentor
  • Hands‑on experience with RTL design and a firm understanding of how it integrates into the overall ASIC design flow
  • Strong analysis, problem solving, and communication skills

Pay

Expected Base Pay Range (USD) 35 - 70, $ per hour. The successful candidate’s starting base pay will be determined based on job‑related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Benefits

Marvell is committed to providing exceptional, comprehensive benefits that support employees at every stage – from internship to retirement and through life’s most important moments. Offerings are built around four key pillars: financial well‑being, family support, mental and physical health, and recognition. Highlights for interns include medical, dental, and vision coverage, perks and discounts, robust mental health resources to prioritize emotional well‑being, and paid holidays. Additional compensation may be available for intern PhD candidates.

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