Digital IC Design Intern, BS - Summer 2027

About the role

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Marvell’s Digital IC (or Digital Logic) Design teams span across multiple domains, giving you the opportunity to work on technologies that power next-generation cloud, AI, storage, and networking solutions. Some teams are responsible for the design and verification of high-performance Ethernet PHY chips. Other teams shape the micro-architecture of the blocks, accelerators and subsystems that make up a system-on-chip (SoC). Across all groups, you’ll collaborate with your direct team and cross-functional partners (across architecture, physical design, design verification, and more) to deliver robust, scalable solutions that enable Marvell’s leadership in data infrastructure.

Responsibilities

• Deep dive into the digital design and implementation of real chip design efforts
• Develop and verify detailed, high-performance RTL design blocks and apply the digital design specifications for high-speed connectivity devices and next-generation chips
• Conduct synthesis, static timing analysis, timing signoff, and power analysis
• Debug design issues and ensure functional correctness
• Investigate & execute new design techniques & flows, and explore emerging methodologies to improve design quality, efficiency, & productivity
• Collaborate with chip architecture, design verification, & physical design teams to solve complex problems and contribute to a team building real products

Requirements

• Currently enrolled in a Bachelor’s Degree in Electrical Engineering, Computer Engineering, or a related field with an expected graduation date between Fall 2027 – Summer 2028
• Completed courses focusing on circuit design, circuit theory, digital logic design, static timing analysis, computer architecture, Verilog, VLSI, digital signal processing (DSP), SoC/ASIC design, or electronics
• Proficiency in programming & scripting languages like Python, Perl, Tcl
• Experience using tools like Synopsys (Primetime), Cadence (Virtuoso & Spectre X), and Mentor
• Hands-on experience with RTL design and a firm understanding on how it integrates into the overall ASIC design flow
• Strong analysis, problem solving, and communication skills

Pay

Expected Base Pay Range (USD) 30 - 59, $ per hour. The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.