Sr Staff ASIC Design Verification Engineer

About Us

At Palo Alto Networks®, we’re united by a shared mission—to protect our digital way of life. We thrive at the intersection of innovation and impact, solving real-world problems with cutting-edge technology and bold thinking. Here, everyone has a voice, and every idea counts. We weave AI into the fabric of everything we do and use it to augment the impact every individual can have.

We believe collaboration thrives in person. Most of our teams work from the office full time, with flexibility when it’s needed. This model supports real-time problem-solving, stronger relationships, and the kind of precision that drives great outcomes. Office-based employees are expected to be in the office four days per week, with one day working remotely.

About the Role

As a Design Verification Engineer on the ASIC team, you will ensure that the ASICs in our next-generation firewall products meet or exceed industry-leading requirements for features, performance, and reliability. You will define verification methodologies, architect test benches, write test plans, specify coverage, write tests, and debug across diverse platforms including simulation, emulation, formal verification, and silicon validation.

Responsibilities

• Collaborate with engineers in software, architecture, design, and verification teams to create comprehensive pre-silicon verification plans across simulation, emulation, and formal verification.
• Plan and execute every aspect of simulation test plans using sophisticated coverage-driven, constrained-random methodologies.
• Develop flows, methodologies, and infrastructure for emulation.
• Create, run, and debug emulation tests in close collaboration with system architects, software engineers, and ASIC designers.
• Define new tools and methodologies to continuously improve quality and velocity.
• Create powerful programs in Python to automate triage, coverage closure, and metrics-driven verification.

Requirements

• BS in EE, CE, or CS required (or equivalent military experience); MSEE preferred.
• Minimum 3 years of experience in ASIC design verification.
• Demonstrated success in taking multiple ASIC products from concept to mass production.
• Expertise in SystemVerilog and UVM.
• Technical strength in the following areas:
  • Defining test plans, including comprehensive adversarial testing.
  • Developing rich functional coverage models.
  • Creating powerful and scalable test benches.
  • Implementing sophisticated self-checking infrastructure with reference models and scoreboards.
  • Developing reusable constrained-random tests.
  • Debugging failures.
  • Closing coverage.

Preferred Skills

• Networking and cybersecurity.
• Formal property verification.
• Silicon validation—bring-up, test, debug, and regression.
• Creating models in Python and C/C++.
• Writing driver code in C.
• Writing powerful, modular, and scalable programs in Python, Perl, and UNIX shell to automate verification tasks, especially regression testing.
• Strong leadership, collaboration, and communication skills.
• Demonstrated ownership and independence in planning, debugging complex failures, closing metrics-driven tasks, driving vendors, and reporting status.

Pay

The starting base salary for this position is expected to be in the range of $106,400.00 - $172,150.00 per year, depending on qualifications, experience, and work location. The offered compensation may also include restricted stock units and a bonus.

Benefits

A description of our employee benefits may be found here.

This role is eligible for immigration sponsorship.