Sr. Principal SoC Power Management Architect

About the role

As a Sr. Principal SoC Power Management Architect, you will drive SoC-level Power Management Architecture. You’ll work with the business unit to understand product requirements and drive SoC and IP-level specifications, partnering with product and cross-functional teams to deliver robust, data-driven solutions where power is a constrained resource. You will collaborate with various SoC global and IP teams to meet product power, performance, and energy efficiency targets.

• Own end-to-end power management architecture, translating business power/performance goals into actionable SoC and IP requirements.
• Drive SoC and subsystem power management architecture, partnering with the Product Power Management Architect to translate product requirements into implementable approaches.
• Assess and expand IP power capabilities with subsystem architects—identify gaps and define new features using data-driven analysis.
• Make HW/SW/FW trade-offs to deliver feasible, performant, and verifiable power management solutions.
• Provide technical direction and architectural reviews leadership, with clear progression toward Lead Power Management Architect for the SoC and ownership of roadmap decisions and alignment.
• Enable HW–SW codesign execution by partnering with senior architects and firmware developers to ensure integration matches architectural intent.
• Provide technical direction to pre- and post-verification teams to deliver high-quality work products (architecture definition, documentation, Si).

Requirements

• 8+ years of proven, hands-on power architecture and SoC low-power expertise, including how architectural decisions map to DVFS/power-state control, power-state residency, and performance-per-watt trade-offs.
• Deep HW development experience, from specification to integration of low-power features, with familiarity in RTL-level design and verification constraints.
• Proven power optimization expertise, using measured results to improve SoC/IP power-saving effectiveness and validate net impact on performance and energy.
• Expert knowledge of SoC low-power modes and IP low-power capabilities, covering power modes/states, wake-up/latency, and retention behavior.
• Ownership of SoC-level low-power management flows, orchestrating subsystem entry/exit and power sequencing for robust behavior across corner cases and workloads.
• Cross-functional leadership and communication, partnering with firmware/software/verification teams to ensure low-power architectural intent is delivered, validated, and maintained.

Skills

Additional skills highly desired:

• Familiar with SW/FW
• Microcontrollers
• HW/SW Co-Design
• ARM Architecture
• Power States

Qualifications

BS degree in Electrical Engineering, Computer Engineering, or Computer Science & 12 years of related experience, MS degree & 8 years, or PhD & 5 years.

Pay

The full base pay range for this role is between $225,500 and $338,500, except in the San Francisco Bay Area where the range is between $237,000 and $356,000.

Benefits

• Premium medical, dental, and vision insurance, as well as income protection and a 401K retirement plan.
• Unlimited flextime and 10+ paid holidays.
• A variety of healthy snacks, energizing espresso, and refreshing drinks.