Sr. Principal I/O SoC Architect

About the role

As a Sr. Principal I/O SoC Architect, you will strategically own and lead the I/O subsystem architecture for next-generation server-class SoCs—finalizing the next-generation Ampere I/O and interconnect architecture and guiding execution for one or more critical subsystems. As the technical authority for high-speed interfaces, with a focus on advanced Ethernet solutions, you will make incisive, data-driven decisions that align and optimize across interacting subsystems.

• Architect the overall I/O subsystem, defining the strategy for data movement, on-chip interconnects, and external interfaces for next-generation SoCs.
• Drive the architecture and integration of multi-gigabit Ethernet IP, prioritizing Time-Sensitive Networking (TSN) functionality.
• Own the end-to-end solutions for the latest USB ecosystem, guiding IP selection and integration across USB 3.x/USB4.
• Evaluate and select third-party IP for high-speed protocols, performing detailed analysis and making data-driven recommendations.
• Collaborate closely with SoC architects, verification, physical design, and software teams to ensure the IO subsystem integrates successfully and meets system-level goals.
• Author and maintain detailed architecture specifications and documentation.
• Mentor junior engineers and serve as the go-to expert for high-speed IO protocols across the company.

Requirements

• 8+ years of proven SoC design or architecture experience, with a significant focus on I/O subsystems.
• Deep, hands-on experience architecting and integrating Ethernet IP, with proven expertise in Time-Sensitive Networking (TSN) standards (e.g. IEEE 1588 and 802.1AS) and applications.
• Strong track record delivering designs using the USB protocol stack across USB3.x and USB4, addressing complex high-speed interoperability and integration issues.
• Solid understanding for I/O SoC architecture fundamentals, including on-chip interconnects (e.g., AXI/CHI), DMA engines, and memory subsystems.
• Experience across the full IP lifecycle, from selection and integration to silicon validation and debug.
• Additional skills highly desired: PCIe (Gen4/5/6); MIPI (C-PHY/D-PHY), DisplayPort; High-speed Memory Interfaces (LPDDR4/5, DDR4/5); SerDes PHY Integration; SI/PI.

Qualifications

BS degree in Electrical Engineering, Computer Engineering, or Computer Science & 12 years of related experience, MS degree & 8 years, or PhD & 5 years.

Pay

The full base pay range for this role is between $225,500 and $338,500, except in the San Francisco Bay Area where the range is between $237,000 and $356,000.

Benefits

• Premium medical insurance, dental insurance, vision insurance.
• Income protection and a 401K retirement plan.
• Unlimited Flextime and 10+ paid holidays.
• A variety of healthy snacks, energizing espresso, and refreshing drinks.