Sr. Principal Front-End Design Automation Engineer

Ampere is a semiconductor design company leading the future of computing with an innovative approach to CPU design focused on high-performance, energy-efficient AI compute. As part of the Softbank Group, we drive sustainable computing for AI, Cloud, and edge applications.

About the Role

As a Sr. Principal Front-End Design Automation (EDA/DevOps) Engineer, you will strategically partner with Ampere’s RTL and Verification organizations to drive measurable gains in pre-silicon productivity through scalable automation, systems, and platform capabilities. You will lead cross-functional initiatives spanning hardware, software, and IT, aligning with design, verification, EDA, and IT stakeholders. You will provide expert guidance for EDA tooling and Ampere flows, architect internal tools, automate end-to-end workflows across on-prem and cloud, and scale infrastructure to improve design quality and expand AI impact in verification and design.

Responsibilities

• Provide expert technical guidance for EDA tools and Ampere design/verification flows, establishing standards and mechanisms that measurably improve productivity and reliability.
• Collaborate with RTL design and verification teams to define and deploy new or improved methods of work.
• Architect, document, deploy, and administer custom Ampere automation and services that streamline RTL design and verification, reducing cycle time and operational overhead for design teams.
• Enable and support EDA tools used for RTL design and verification (SystemVerilog simulation, Lint, CDC, RDC, UPF, debug).
• Partner with IT, EDA vendors, RTL design, and verification teams to deliver high-performance, efficient solutions.
• Drive AI-enabled automation for design and verification, accelerating analysis and decision-making while improving coverage and issue resolution speed.

Requirements

• 8+ years of proven Front-End Design Automation (EDA/DevOps) expertise in the technology sector (semiconductor design preferred).
• Highly talented Python or Perl scripting skills.
• Strong SystemVerilog language expertise with background in DV/UVM/Coverage/Simulation/Debug and/or RTL static checks (Lint/CDC/RDC/UPF).
• Solid experience with IP and SoC RTL design and verification workflows.
• Proven experience with HPC scheduling/workload management, like IBM LSF (Load Sharing Facility) or SLURM (Simple Linux Utility for Resource Management), for running EDA workloads.
• Additional skills highly desired: SCM/Source Code Management; Git/Perforce; RDBMS; CI/CD; Cloud Computing.

Qualifications

• BS degree in Electrical Engineering, Computer Engineering, or Computer Science & 12 years of related experience,
• MS degree & 8 years of related experience, or
• PhD & 5 years of related experience.

Benefits

• Premium medical, dental, and vision insurance, as well as income protection and a 401K retirement plan.
• Unlimited flextime and 10+ paid holidays for a healthy work-life balance.
• A variety of healthy snacks, energizing espresso, and refreshing drinks.

Pay

The full base pay range for this role is between $225,500 and $338,500.