Principal Design Automation Engineer

About the role

As a Staff/Principal Design Engineer in the NVE Design Engineering organization at Micron Technology, you will drive the transformation of NAND circuit development through design automation, agentic circuit-design enablement, and environment transition. You will implement core Xpath, Ypath, and Array design during project execution and collaborate with project teams to integrate Core schematics into full-chip schematics, validating design performance and functionalities through block and chip-level simulations using standard industry simulators.

You will also implement analog and mixed-signal circuit design (charge pumps, op amps, DACs, ADCs, linear regulators, oscillators, bandgap, LDO, thermometers, page buffers, PDNs, level shifters, IO buffers, RTL, Verilog) to meet specifications and validate performance via simulations.

Serve as a technical authority across analog/core teams, solving sophisticated technical problems at the intersection of circuit behavior, modeling, simulation methodology, and automation reliability.

Responsibilities

• Develop and productize agentic enablement for circuit design, including AI/LLM-assisted flows supporting:
  • Environment setup and self-healing configuration
  • Guided simulation and debug
  • Intelligent corner planning and coverage closure
  • Automated schematic/layout checks and review assistance
  • Documentation synthesis and knowledge retrieval from internal sources
  • Block/subsystem/full-chip verification (analog/mixed-signal), including reproducible run recipes, golden reference management, and regression gating criteria
• Integrate automation with project execution, partnering with circuit designers, firmware, validation, and architecture teams to align tooling with breakthrough needs and deliver measurable cycle-time reduction.
• Collaborate with multi-functional team members (Product Engineering, Test, Probe, Process Integration, Assembly, Marketing) to ensure automation and environment choices support manufacturability, testability, reliability, time-to-market, and customer satisfaction.
• Implement analog and mixed-signal circuit design and layout (page buffers, block selectors, Xdecoder, Ydecoder, bias table and waveforms, PDNs, level shifters, charge pumps, op amps, DACs, ADCs, linear regulators, oscillators, bandgap, IO buffers, RTL, Verilog).
• Validate design performance and functionalities through block and chip-level simulations using industry-standard simulators.
• Guide layout planning, parasitic extractions, and ensure compliance with semiconductor reliability standards (CHC, NBTI, stress, snapback, Electromigration, and IR analysis).

Requirements

• MS (PhD preferred) in Electrical Engineering.
• 8+ years of NAND design-relevant experience with proficient knowledge of NAND Flash memory read, program, and erase algorithms.
• Proficiency in analog/mixed-signal circuit design and layout (page buffers, block selectors, Xdecoder, Ydecoder, bias table and waveforms, PDNs, level shifters, charge pumps, op amps, DACs, ADCs, linear regulators, oscillators, bandgap, IO buffers, RTL, Verilog).
• Strong fundamentals in semiconductor and device physics, including understanding of reliability issues (CHC, NBTI, stress, snapback, Electromigration, and IR analysis).
• Proficiency in circuit verification and optimization, layout planning, and parasitic extractions.
• Experience with circuit design verification flows, including block-level, subsystem-level, and full-chip simulations, corner management, PVT/mismatch analysis, and results qualification.
• Proficiency with analog and digital simulators such as HSPICE, Fast SPICE, and Verilog.
• Proven proficiency in Python for engineering automation, including development of maintainable scripts, libraries, or frameworks that collaborate with EDA tools for simulation control, data extraction, regression management, or reporting.
• Proficiency with Cadence design tools, LVS/DRC tools, and UNIX.

Pay

The US base salary range for this full-time position is $176,000.00 - $298,000.00 per year. Additional compensation may include benefits, bonuses, and equity. Individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure, and relevant education or training.

Benefits

• A choice of medical, dental, and vision plans tailored to meet family healthcare needs and budget.
• Income protection programs if unable to work due to illness or injury, and paid family leave.
• A robust paid time-off program and paid holidays.

For additional information, see the Benefits Guide.