Sr. Principal DFT Engineer (AI2533)

About the role

SiMa.ai™ is scaling Physical AI in Robotics, Automotive, Industrial, Aerospace and Defense, and Medical markets. We have created the industry's best purpose-built, software centric Physical AI HW/SW platform that leads the industry in Ease of use, performance, and power efficiency. SiMa.ai is led by technologists and business veterans backed by a set of top investors committed to helping customers bring ML on their platforms. SiMa.ai was founded in 2018, has raised $355M and is backed by Fidelity Management & Research Company, Maverick Capital, Point72, MSD Partners, VentureTech Alliance and more.

We're looking for a Sr. Principal-level DFT leader to own that foundation. This isn't a role focused on executing someone else's test plan — you'll be the person defining how SiMa approaches Design for Test at the architecture level, then staying hands-on through execution, tape-out, and pattern bring-up across our next generation of SoCs.

Responsibilities

• Set the DFT architecture and methodology strategy for SiMa's upcoming industrial, robotic, and automotive ICs — decisions that ripple through every downstream team touching the chip.
• Drive execution of that strategy directly, working shoulder-to-shoulder with RTL design, verification, and physical design teams to make sure the architecture you've defined actually holds up in silicon.
• Serve as a technical anchor for the broader DFT team — enabling their success day to day, unblocking hard problems, and raising the technical bar across the group.
• Own the whole DFT lifecycle, not one slice of it — architecture through tape-out through pattern bring-up, on advanced finFET nodes, across multiple ICs.

Requirements

• BSEE with 18+ years of experience or MSEE/PhD with 16+ years of experience.
• Commanding knowledge of all aspects of DFT.
• Experience with end-to-end DFT execution from architecture to tape-out to pattern bring-up across multiple ICs in advanced finFET technology.
• In-depth knowledge of VLSI design as well as hardware description languages such as Verilog and System Verilog.
• Deep hands-on experience with latest EDA tools like Synopsys SMS/Testmax or Mentor Tessent.
• Good working knowledge of non-DFT EDA tools like VCS/Verdi, Fusion Compiler, PrimeTime, PrimePower, RedHawk, StarRC, etc. is preferred.
• Strong problem solving and debug capabilities.
• Proficient at working with cross functional and cross site teams.
• Good communication skills, self-driven, and a good team player.

Personal Attributes

• Can-do attitude.
• Strong technical leadership attributes.
• Curious, creative, and good at solving problems.
• Execution and results oriented.
• Self-driven, thinks big and is highly accountable.
• Good communication skills.

Pay

The annual salary for this position ranges from $231,100 – $358,200. The actual annual salary offered will depend on several factors, including job-related skills, experience, technical expertise, qualifications, work location, and business needs. In addition to base salary, this role is also eligible for private company equity and a comprehensive package of employee benefits. Please note that the salary range listed reflects base salary only and does not include equity or other forms of compensation.