Jobs · Engineering

Principal DFT Engineer

SambaNova · San Jose, CA · 1 wk ago
RemoteRemoteEngineering$180k–$255k/yrFull-time

About the role

SambaNova is looking for a talented and motivated Principal Design for Test (DFT) Engineer to help build state-of-the-art RDU chips for machine learning and artificial intelligence. We are seeking a highly hands-on engineer responsible for DFT architecture and implementation, verification, ATPG, MBIST, and silicon bring-up for complex high-performance chips.

Responsibilities

  • Define & implement block-level and SoC-level DFT architecture for large, hierarchical SoCs.
  • Develop and maintain ATPG flows for stuck-at, at-speed, and advanced fault models.
  • Develop scripts and automation for DFT insertion, ATPG, coverage analysis, pattern generation, and debug.
  • Develop and maintain JTAG, IEEE 1500, and IEEE 1687/IJTAG infrastructure for internal test and debug access.
  • Generate production-quality ATPG and MBIST patterns and support deployment to ATE.
  • Work closely with STA and Physical Design teams on DFT timing closure.
  • Support silicon diagnosis, failure localization, yield analysis, and manufacturing test optimization.

Requirements

  • B.S. in computer science, computer engineering, or related field.
  • 10+ years of relevant industry experience.
  • Deep understanding of scan insertion, scan compression, ATPG, MBIST, JTAG, and hierarchical DFT.
  • Hands-on experience with Siemens Tessent tool flow (preferred) or equivalent industry-standard DFT tools.
  • Familiarity with cell-aware ATPG, small-delay defects, IEEE 1500, IEEE 1687/IJTAG, and low-power DFT is highly desirable.
  • Strong understanding of advanced ATPG, silicon diagnosis, and failure localization methodologies.
  • Experience with STA constraints & analysis for DFT modes & SDF simulations.
  • Working knowledge of Verilog/System-Verilog simulators & waveform debugging.

Preferred Qualifications

  • Experience with ATE pattern deployment and silicon bring-up.
  • Experience with multi-die/chiplet DFT, known-good-die test, or die-to-die interface testing.
  • Experience with large compute, AI accelerator, or HPC SoCs.

Pay

Base salary range: $180,000—$255,000 USD

Benefits

  • 95% premium coverage for employee medical insurance, and 77% premium coverage for dependents.
  • Health Savings Account (HSA) with employer contribution.
  • Dental, Vision, Short/Long-term Disability, Basic Life, Voluntary Life, and AD&D insurance plans.
  • Flexible Spending Account (FSA) options: Health Care, Limited Purpose, and Dependent Care.
  • Well-being benefits including a full subscription to Headspace, Gympass+ membership, One Medical membership, counseling services with an Employee Assistance Program, and more.

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