Sr. Physical Design CAD Engineer

About the role

This is a great opportunity to develop and maintain world-class hardware physical design flow in a fast-paced production environment on the very edge of modern technology! The goal of our Silicon CAD team at AMD is to determine a set of standards and techniques for designing chips with the highest performance, lowest cost, and lowest power usage. We then automate these best practices into a software design flow for efficiency and consistency, and work with various design teams to put the software to use in constructing next-generation GPUs, CPUs and APUs with industry-standard EDA software tools such as Synopsys IC Compiler II, Fusion Compiler and Primetime.

Responsibilities

• Develop, maintain, and enhance Physical Design CAD flows supporting AMD's AI, HPC, CPU, GPU, and SoC programs.
• Deploy and support industry-standard EDA tools and methodologies across multiple design projects.
• Develop innovative Physical Design solutions for place-and-route, timing closure, power optimization, and design convergence.
• Debug and optimize physical design challenges related to power, performance, and area (PPA).
• Create and maintain validation environments, test suites, regression infrastructure, and qualification methodologies.
• Evaluate, qualify, and integrate new EDA tool capabilities and vendor technologies.
• Collaborate closely with design teams to improve methodology efficiency, scalability, and productivity.
• Work directly with EDA vendors, including Synopsys and Cadence, to drive tool enhancements and future roadmap requirements.
• Improve and maintain CAD infrastructure, automation frameworks, and engineering workflows.
• Leverage AI technologies, automation, and intelligent workflows to improve productivity, reduce design cycle time, and increase engineering efficiency.
• Provide technical guidance, customer support, and methodology expertise to engineering teams worldwide.

Preferred Experience

• Strong experience with Physical Design implementation and CAD flow development.
• Hands-on expertise with Synopsys Fusion Compiler, Cadence Innovus, and PrimeTime.
• Experience with physical verification, extraction tools (StarRC or equivalent), and timing signoff.
• Deep understanding of power, performance, and area (PPA) optimization.
• Strong TCL and Python scripting skills for automation and tool development.
• Experience supporting multiple chip tape outs and production design environments.
• Ability to debug and solve complex Physical Design flow and methodology issues.
• Experience working directly with EDA vendors such as Synopsys or Cadence.
• Demonstrated use of AI tools or automation to improve engineering productivity.
• Strong communication, collaboration, and problem-solving skills.

Qualifications

Bachelor’s or master’s degree in electrical engineering, Computer Science, or equivalent is preferred.