Sr. Staff Physical Design Engineer

Responsibilities

• Implement digital blocks in advanced tech nodes from synthesis through physical verification, using industry standard tools and flows
• Drive full-chip STA signoff, review constraints, debug timing reports and implement ECO
• Drive power analysis and optimization while balancing area and performance trade-offs
• Drive full-chip floor planning, IO placement and clock distribution
• Understand clock details and customize clock implementation for functional and test clocks
• Debug and clean up DRC/LVS, Functional and timing ECO implementation
• Work with EDA companies to resolve any tool issues
• Write TCL, Python, or Shell scripts to automate flow or customize existing flows

Qualifications

• Bachelor’s in Electrical Engineering or Computer Engineering
• 12+ years of industry experience working as a Physical Design Engineer
• Must have completed blocks or top-level physical design for large ASICs or mixed signal chips that taped out
• Thorough knowledge of timing closure, LVS/DRC closure
• Experience in TCL and Python (or other scripting languages)
• Strong teamwork skills with the ability to collaborate with multiple functional teams across a variety of fields
• Able to react to change and thrive in a fast-paced environment

Preferred Qualifications

• Masters Electrical Engineering or Computer Engineering with 8 years of industry experience
• Hands-on experience with Cadence tools
• Tape-out experience with 3nm designs
• Be willing to do manual layouts as well as willingness to learn and do silicon photonics layout
• EM/IR analysis using standard industry signoff tools

Benefits

• Comprehensive Health Care Plan (Medical, Dental & Vision)
• Retirement Savings Matching Program
• Life Insurance (Basic, Voluntary & AD&D)
• Generous Time Off (Vacation, Sick & Public Holidays)
• Paid Family Leave
• Short Term & Long Term Disability
• Training & Development
• Commuter Benefits
• Flexible, hybrid workplace model
• Equity grants (applicable to full-time employees)