Sr. Package Layout Engineer, Annapurna Labs - AI Silicon Packaging

About the role

Annapurna Labs (our organization within AWS) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.

Responsibilities

• Lead the full package layout cycle from die floor planning, bump/pad assignment, and RDL routing through substrate design, verification, and tape out release.
• Drive physical design of advanced packaging architectures including 2.5D interposer, 3D-IC, fan-out wafer-level packaging, and silicon bridge technologies (e.g., CoWoS, EMIB, or similar).
• Define and optimize package floorplans considering die placement, bump maps, power/ground distribution, high-speed signal escape routing, and decoupling capacitor placement.
• Perform detailed RDL and substrate routing for high-density interconnects including microbumps, C4 bumps, TSVs, microvias, and PTH vias across multi-layer organic substrates and silicon interposers.
• Participate in die-level RDL routing and bump planning in coordination with ASIC physical design teams, ensuring the die-package interface is co-optimized for power delivery and signal routing from the earliest design stages.
• Drive cross-level layout co-optimization across die RDL, interposer/substrate, and PCB levels to achieve the best overall power delivery network and high-speed signaling performance, minimizing impedance discontinuities and routing bottlenecks at each interface boundary.
• Create and enforce package design rules and guidelines, working with OSAT partners and foundries to ensure DFM compliance and high yield.
• Run and review physical verification checks (DRC, connectivity, shorts/opens) and drive design closure with zero escapes.
• Manage package design schedules, milestones, and deliverables, coordinating across multiple concurrent projects and tape out cycles.
• Collaborate with SI/PI engineers to incorporate electrical constraints into the physical layout — impedance-controlled routing, power plane optimization, and critical net shielding.
• Interface with OSAT vendors and foundry partners on substrate and interposer manufacturing feasibility, design rule negotiations, and process capability alignment.
• Identify packaging technology risks early and propose design or process mitigations to ensure reliability and manufacturability.
• Mentor junior layout engineers and contribute to the development of team best practices, automation flows, and design reuse strategies.

Qualifications

• Bachelor's degree in Electrical Engineering or a related field
• 10+ years of experience in IC package layout and physical design
• Proven track record of leading package designs from concept through tape out for complex, multi-layer organic substrates or silicon interposers
• Hands-on expertise with package layout tools such as Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition, or equivalent
• Deep understanding of advanced packaging technologies: 2.5D/3D-IC, fan-out WLP, RDL, TSV, microbump, and silicon bridge interconnects
• Strong knowledge of package design rules, DFM constraints, and physical verification methodologies (DRC, connectivity checks)
• Familiarity with substrate and interposer manufacturing processes, material properties, and their impact on design decisions