Sr. Formal Verification Engineer, Amazon Leo

About the role

The Design Verification team within Amazon's Leo Silicon Team is seeking a Senior Formal Verification Engineer to lead formal verification efforts on complex modem SoC designs. This role involves developing and executing formal verification strategies, driving proof convergence, and championing a "formal-first" verification strategy.

Responsibilities

• Develop and execute formal verification strategies using JasperGold and/or Questa Formal for property checking (FPV), connectivity checking (CC), register verification, and sequential equivalence checking (SEQ)
• Write, review, and debug SystemVerilog Assertions (SVA) to verify complex modem SoC design behaviors across NOC, interconnect, modem IPs, and control logic
• Drive convergence on formal proofs by applying abstraction techniques, complexity reduction strategies, and assume-guarantee reasoning
• Collaborate with RTL designers, architects, and simulation-based DV engineers to define verification plans that incorporate formal methods alongside UVM-based simulation and emulation approaches
• Champion a "formal-first" verification strategy by identifying and pursuing opportunities to apply formal verification to new design blocks
• Develop reusable formal verification infrastructure, including constraint libraries, parameterized property templates, and automated regression flows integrated into our CI/CD verification pipeline
• Contribute to coverage closure strategies by leveraging formal coverage analysis to complement simulation-driven functional coverage
• Mentor and guide DV engineers in formal verification techniques, SVA best practices, and proof convergence strategies
• Partner with EDA vendors to evaluate new formal verification capabilities and drive tool improvements that benefit the team

Requirements

• Bachelor's degree in electrical engineering, computer engineering, or equivalent
• 8+ years of experience in ASIC/SoC design verification with a strong focus on formal verification
• Experience with JasperGold and/or Questa Formal
• Strong proficiency in SystemVerilog Assertions (SVA) and formal property specification
• Experience with formal verification applications: FPV, connectivity checking, register verification, equivalence checking, and coverage analysis
• Demonstrated ability to drive proof convergence on complex designs using abstraction, case-splitting, and assume-guarantee techniques
• Proficiency in SystemVerilog and UVM concepts
• Proficiency in leveraging AI/LLM tools to accelerate formal verification workflows including AI-assisted SVA generation, property debugging, proof exploration, and automated constraint refinement

Qualifications

• Bachelor's degree in electrical engineering, computer engineering, or equivalent
• 8+ years of experience in ASIC/SoC design verification with a strong focus on formal verification
• Experience with JasperGold and/or Questa Formal
• Strong proficiency in SystemVerilog Assertions (SVA) and formal property specification
• Experience with formal verification applications: FPV, connectivity checking, register verification, equivalence checking, and coverage analysis
• Demonstrated ability to drive proof convergence on complex designs using abstraction, case-splitting, and assume-guarantee techniques
• Proficiency in SystemVerilog and UVM concepts
• Proficiency in leveraging AI/LLM tools to accelerate formal verification workflows including AI-assisted SVA generation, property debugging, proof exploration, and automated constraint refinement

Benefits

• Comprehensive benefits including health insurance, retirement plans, paid time off, and parental leave
• Amazon's inclusive culture empowers Amazonians to deliver the best results for our customers