Sr. Engineer, SoC Design Verification

About the role

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a SoC Design Verification Engineer to lead pre-silicon verification of the Beowulf SoC, with focus on the Compute Subsystem (CSS), DDR memory subsystem, and Fabric NoC. This role will drive coverage, coherency, memory traffic, connectivity, error handling, and bring-up features critical to silicon success. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Responsibilities

• Develop and own scalable verification environments for Beowulf SoC CSS, DDR, and Fabric NoC across subsystem and full-SoC levels.
• Write, refine, and execute test scenarios for compute operation, memory initialization and traffic, coherency, routing, ordering, QoS, power management, error handling, and data movement.
• Analyze coverage gaps, debug failures, drive root-cause analysis, and collaborate closely with architecture, RTL, firmware, emulation, and system teams.
• Drive verification planning, regression quality, coverage closure, and signoff for major SoC features.
• Automate verification flows using scripting, reusable infrastructure, and AI productivity tools.
• Mentor engineers and contribute to verification methodology and design-for-verification improvements.

Requirements

• Deeply curious about SoC architecture, compute systems, DDR behavior, and Fabric NoC/interconnect verification.
• Expert in UVM, SystemVerilog, coverage-driven verification, assertions, and subsystem-level debug.
• Experienced in verifying compute subsystems, DDR controllers and PHY-facing logic, NoC/interconnect protocols, coherency, ordering, and data movement.
• Comfortable with reset, power management, error handling, performance, and high-concurrency system scenarios.
• Proactive, detail-oriented, and effective in cross-functional technical discussions.

Skills

• Familiar with Python, C/C++, Tcl, CocoTB, or similar verification automation tools.

Pay

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Schedule

This role is hybrid, based out of Boston, MA; Toronto, ON; or Santa Clara, CA.