SoC HW (Digital, Analog or PnP) Validation Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions.

Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing, and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more.

About the role

The post-silicon validation team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale, and sustainability related to Microsoft cloud hardware. We are looking for a SoC HW (Digital, Analog or PnP) Validation Engineer to join the team and help manage and optimize the Cloud infrastructure.

Responsibilities

• Own post-silicon validation of one of the following areas: functional, electrical, or power/performance.
• Define, guide, and contribute to the implementation of silicon debug tools and capabilities.
• Ramp up on the overall architecture, implementation of complex features/flows/protocols, and their interactions with other parts of the SoC, with the platform, and with software.
• Provide technical guidance, coaching, and mentorship to other engineers in your areas of expertise.
• Develop validation strategy, requirements, environments, tools, and methodologies including debug board and hardware/software requirements.
• Apply your knowledge of validation principles and techniques and your judgement to write test plans and implement them by developing test content, scripts, tools, and other validation collateral.
• Execute content in post-silicon, triage, and debug failures.
• Apply your growth mindset to learn and adapt in a complex and dynamic environment.
• Engage with partners to drive continuous improvement to the design, validation plans/collateral, and methodology to prevent, reduce, and/or find bugs sooner, more easily, or more reliably.
• Apply your One Microsoft mentality to collaborate with and influence architects, logic designers, verification engineers, other post-silicon validators, and IP and tool providers.
• Delight your customers by providing high-quality results on schedule.
• Provide technical leadership with respect and integrity.
• Apply your expertise towards pre-silicon verification plans, tests, and debug of your area.

Requirements

• Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience OR equivalent experience.
• Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check every two years.
• This role requires access to export-controlled information; proof of citizenship, U.S. residency, or other protected status is required.

Qualifications

• Applied understanding of Computer Architecture and CPU/SoC validation principles, including:
  • Understanding of SoC subsystem, SoC system level, and platform level functionality.
  • Writing scripts/software with industry standard languages like Python or C/C++.
• Proficient communication, collaboration, and teamwork skills with ability to lead, grow, and contribute to diverse and inclusive teams.
• Verification, logic development, validation, or validation tools experience as part of a CPU, SoC, and/or IP development team.
• Leadership skills.
• Demonstrated validation expertise in one or more of the following:
  • Functional: Core, cache Coherency/mesh/fabric, PCIe/IO, Memory Controller, Power Management.
  • Power and Performance.
  • Automation, Content Creation, or Tools/Scripts Development.
• Validation of:
  • Ability to develop synthetic SoC validation Core, Coherency, Memory, and IO content to run on both bare metal and OS environments.
  • Ability to develop sophisticated tools/scripts to support SoC validation debug activities such as crash dumps and register dumps.
  • Understanding system level software and firmware.
• Experience running silicon content on pre-silicon platforms such as emulation or FPGA.
• Demonstrated success in hardware/software debug efforts.
• Hands-on expertise debugging silicon failures using on-chip debug features (like trace or JTAG) as well as test equipment (like protocol analyzers, bit error rate testers, logic analyzers, oscilloscopes).

Preferred Qualifications

• Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ years technical engineering experience OR Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field OR equivalent experience.

Pay

• The typical base pay range for this role across the U.S. is USD $102,100 - $202,200 per year.
• For specific work locations within the San Francisco Bay area and New York City metropolitan area, the base pay range is USD $133,800 - $219,200 per year.
• Certain roles may be eligible for benefits and other compensation.

Find additional benefits and pay information here.