Senior SoC HW (Power Management) Validation Engineer

About the Role

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure, powering the “Intelligent Cloud” mission. SCHIE delivers core infrastructure and foundational technologies for over 200 online businesses, including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and Microsoft Azure. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE designs, develops, manufactures, and packages state-of-the-art computer chips, notably the Azure Cobalt. We are seeking a Senior SoC HW (Power Management) Validation Engineer to join the post-silicon validation team, ensuring robust, efficient, and scalable power management solutions for Microsoft's cloud infrastructure.

Responsibilities

• Own post-silicon validation and debug of Power Management features across CPU cores, mesh, memory, I/O, package, and platform power domains.
• Develop and execute comprehensive validation strategies for power states, DVFS, idle and active power management, thermal management, performance-per-watt optimization, and system-level power features.
• Drive root-cause analysis of complex silicon, firmware, hardware, and software issues impacting power, performance, stability, and feature readiness.
• Define validation requirements, test plans, methodologies, automation frameworks, debug tools, and telemetry solutions to improve validation coverage and efficiency.
• Collaborate with architects, design, firmware, verification, system software, and platform teams to ensure first-time-right implementation of power management features.
• Lead silicon bring-up, feature characterization, workload-based validation, and power-performance correlation activities across development milestones.
• Analyze power, performance, and thermal telemetry to identify bottlenecks, validate design assumptions, and optimize platform efficiency.
• Influence pre-silicon verification strategies, coverage plans, and debug methodologies using post-silicon learnings.
• Provide technical leadership, mentoring, and guidance in Power Management architecture, validation techniques, and debug methodologies.
• Drive continuous improvement in validation infrastructure, automation, and debug capabilities to accelerate issue resolution and improve product quality.
• Partner across organizations to deliver high-quality silicon on schedule while meeting aggressive performance-per-watt and power efficiency targets.
• Foster a collaborative One Microsoft culture through technical excellence, ownership, innovation, and integrity.

Qualifications

Required Qualifications:

• Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience.
• OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience.
• OR Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience.
• OR equivalent experience.

Preferred Qualifications:

• Understanding of SoC system-level and platform-level functionality, defining silicon validation requirements, and writing scripts/software in Python or C/C++.
• Strong communication, collaboration, and teamwork skills, with the ability to lead and contribute to diverse and inclusive teams.
• Experience in verification, logic development, analog validation, or validation tools as part of a CPU, SoC, and/or IP development team.
• Leadership skills and demonstrated validation expertise in power validation, performance testing, automation, content creation, or tools/scripts development.
• Ability to develop synthetic SoC validation content for Core, Coherency, Memory, and IO, running on bare metal and OS environments.
• Experience developing tools/scripts for SoC validation debug activities, such as maximum power, current transients, and register dumps.
• Understanding of board-level schematics and system-level software and firmware.
• Experience running silicon content on pre-silicon platforms like emulation or FPGA.
• Demonstrated success in hardware/software debug efforts.

Screening Requirements

• Ability to meet Microsoft, customer, and/or government security screening requirements, including the Microsoft Cloud Background Check and export control regulations.
• Proof of citizenship or protected status for assessment of eligibility to access export-controlled information.

Pay

The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. For specific work locations within the San Francisco Bay area and New York City metropolitan area, the base pay range is USD $160,200 - $261,000 per year. Certain roles may be eligible for additional benefits and compensation. Find more information at https://careers.microsoft.com/us/en/us-corporate-pay.