SoC Architecture and Design Engineer, Senior Member of Technical Staff (SMTS)

About the role

The SoC Architecture and Design Engineer plays a crucial role in the Heterogeneous Integration Group (HIG), focusing on the architecture, design, development, and integration of next-generation High Bandwidth Memory (HBM) System on Chip (SoC) logic dies. This role requires a deep understanding of memory sub-systems, IP integration, and the ability to contribute to robust, high-performance SoC solutions.

Responsibilities

• Architect, design, and implement RTL for SoC-level blocks and subsystems used in HBM logic die.
• Architect and design memory sub-systems including memory IP selection and integration, bus and protocol selection, and power/performance/area optimization.
• Integrate internal and third-party IP (e.g., controllers, microcontrollers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY-adjacent logic).
• Translate architectural and micro-architectural specifications into high-quality RTL implementations.
• Participate in SoC-level integration activities, including clocking, reset, power intent, and configuration infrastructure.
• Assist with pre-silicon validation and post-silicon bring-up, including root-cause analysis of silicon issues.
• Contribute to design documentation, block specifications, and design reviews.
• Collaborate multi-functionally with Product Engineering, Test, Probe, Process Integration, and Manufacturing to ensure robust and manufacturable builds.

Qualifications

• Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, or a related field, with a minimum of 15 years of experience in a related field.
• Proficiency in SystemVerilog/Verilog and familiarity with SoC integration methodologies.
• Experience with the RTL-to-GDS flow, including synthesis, static timing analysis, and develop sign-off considerations.
• Familiarity with EDA tools from Cadence, Synopsys, and/or Siemens.
• Programming or scripting experience (e.g., Python, TCL, Perl, or shell scripting).

Preferred Qualifications

• Experience with HBM, DRAM, or memory-centric SoC designs.
• Familiarity with high-speed interfaces, clocking strategies, reset architectures, and power management concepts.
• Exposure to DFT concepts (scan, MBIST, BIRA/BISR) and debug.
• Experience with hardware emulation or acceleration platforms (e.g., Palladium, Veloce, Zebu).

Pay

The US base salary range that Micron Technology estimates it could pay for this full-time position is $177,000.00 - $334,000.00 a year. Additional compensation may include benefits, bonuses, and equity.