SMTS Physical Design Engineer

Responsibilities

• Floorplanning: Define and implement full chip floorplans in close collaboration with the analog design team — including custom analog block placement, analog/digital partitioning, I/O ring architecture, power domain definition, and block-level area allocation.
• Power Planning: Design and implement the chip power distribution network (PDN); coordinate with the analog team on analog supply isolation, guard ring placement, and substrate noise considerations.
• Place & Route: Execute full-chip place-and-route (Cadence Innovus) from synthesized netlist through routed and optimized database across all required corners and modes.
• Timing Closure: Own static timing analysis (Cadence Tempus) across all PVT corners and modes; identify and resolve timing violations through ECO, placement, and routing optimization; coordinate with the Chip Lead on constraint refinement.
• Power Integrity: Perform IR drop and electromigration analysis (Cadence Voltus or equivalent); identify and resolve PDN weaknesses.
• Physical Verification Sign-off: Execute and close DRC, LVS, and ERC to foundry-clean status using Mentor Calibre; manage waiver process for any non-cleanable violations.
• DFT Integration: Implement scan chain insertion and work with the Chip Lead on ATPG pattern generation and test coverage targets.
• Foundry Coordination: Interface with foundry on PDK questions, fill rule implementation, and tape-out submission requirements.
• Documentation: Maintain PD methodology documentation, floorplan rationale records, and ECO history to support program continuity and follow-on chip development.

Qualifications

• BS, MS, or PhD in Electrical Engineering or related field
• 8–15 years of physical design experience with at least one complete front-to-back tape-out as the primary or lead PD engineer
• Hands-on proficiency with Cadence Innovus for place-and-route — comfortable navigating complex placement constraints, congestion-driven routing, and post-route optimization without step-by-step guidance
• Hands-on proficiency with Cadence Tempus for static timing analysis including MMMC setup, OCV/AOCV analysis, and ECO-driven timing closure
• Hands-on proficiency with Mentor Calibre for DRC, LVS, and ERC sign-off
• Experience placing and integrating hard macros (analog PHY blocks, memory compilers, I/O cells) within a constrained mixed-signal floorplan
• Demonstrated ability to take broad ownership and drive to closure — comfortable leading implementation decisions, working across disciplines, and managing priorities without a large supporting PD organization
• Strong debugging and root-cause analysis skills — the ability to look at a failing DRC deck, a congested routing region, or a timing path that doesn't respond to standard approaches and find a path forward
• Ability to communicate clearly with non-PD engineers — Chip Lead, analog designers, and DV engineers — about physical implementation constraints and their design implications