Senior UCIe PHY Expert, MLA Technology

Key job responsibilities

• Collaborate with architects, design teams, and software engineers on our next generation ML chips
• Support on-going debug and operations of previous ML chips within manufacturing and the data center
• Dive deep into IP integration, packaging, silicon bring up, characterization, and validation of our UCIe subsystems
• Independently develop the scripts you need to execute and collaborate with software engineers as your needs scale

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Systems Engineering, or related fields
• 7+ years of experience in Silicon development
• 3+ years in SOC/IO/Subsystems Experience working closely with physical design teams to develop highly optimized ASICs with excellent power, performance and area
• Good understanding of UCIe at the PHY and controller level
• Good knowledge of UCIe training, timing parameters and/or controller features
• Support the physical design team with IP integration, 2.5D packaging, clocking and timing constraints
• Able to create scripts (lua, bash, python, etc.) to accomplish functional day to day tasks.
• Drive cross-functional triage effort on functional and performance issues
• Take the leadership role in post-silicon bring-up of UCIe-Advanced or Standard
• Perform system-level debug and root-cause analysis through bring-up, characterization, validation and production phases

Preferred Qualifications

• MS degree in computer science, electrical engineering, or related field
• Strong Firmware development skills within embedded environments
• Good leadership skills and ability to multi-task and thrive in a dynamic environment
• Knowledge of UCIe phy and controller related protocols
• Good communication skills and interpersonal skills