Senior Testchip SoC Physical Design Engineer (Integration & Methodology)

About the role

Join the Design Technology Platform (DTP) organization within Intel Foundry as part of the X-Chip SoC Full-Chip Integration team. This team plays a critical role in enabling next-generation semiconductor innovation by delivering testchip platforms that validate advanced process technologies and support high-volume manufacturing readiness.

Responsibilities

• Developing layout design methodology for testchip development in next generation process nodes
• Working closely with Process Integration, Yield and QnR to define critical Design features that need to be exercised in the early lead vehicle test chips
• Establishing, orchestrating, overseeing, and maintaining hierarchical layout design specifications for correct-by-construction integration
• Building and executing tactical plans to converge hierarchical SOC layout design against aggressive schedule requirements by working closely with PDK teams
• Driving all aspects of physical design convergence, including preparing layout hierarchy for design tape-in, debugging and resolving issues uncovered by verification tools
• Working with tool/flow owners and vendors for ongoing tool/methodology improvement

Qualifications

• Master's degree in electrical engineering or related field with minimum of 5 years of experience in physical/layout design in advance technology nodes
• Experience with layout design tools like Cadence Virtuoso Suite or Synopsys Custom Compiler
• Experience with design rules and layout constraints in advanced semiconductor processes
• Experience with floorplanning, hierarchical design integration, and layout verification/debug