Senior Technical Staff Engineer - Design (IO)

Job Description

The successful candidate will join the rapidly growing Data Center Solutions (DCS) business unit at Microchip. DCS has a broad portfolio of products widely deployed by the industry's cutting-edge server/storage OEMs and hyperscale datacenters. Customers deploy DCS solutions into applications ranging from Big Data capacity storage to artificial intelligence and machine learning that are helping to shape the next digital age. Our product portfolio includes SAS/PCIe/NVMe/CXL products that connect, manage, and secure the world’s information, including Flash Controllers, High Performance Switches, RAID Controllers and Memory Controllers. Join a team where you can expand your skill set and drive key elements of the industry’s technology leadership. An opening exists for Tech Staff/Sr. Staff IO Design Engineer with an interest in developing the next generation of storage and memory controller SoC products. This will involve taking a design from initial concept through to production. Throughout you will work beside experienced engineers and be exposed to Microchip’s Best-In-Class engineering practices. Working side-by-side with some of the brightest minds and most innovative people in the industry, you won't just fill a position, you will be given an opportunity to work on a team where your contributions matter.

Requirements/Qualifications

• B.S or M.S degree in electrical engineering with 12+ years related experience.
• Hands-on experience with pad ring planning, IO cell placement, and bump map/pattern definition for advanced SoC designs.
• Knowledge of IO library cells, IO standards, and PHY-level IO interfaces (SerDes, DDR, PCIe, CXL).
• Experience with IO planning and implementation EDA tools (e.g., Orbit IO, ISP or equivalent); specific tool experience is valuable but not mandatory.
• Experience generating and validating IO connectivity deliverables (pad ring DEF, IO netlist, bump assignment) for physical design hand-off).
• Experience with Verilog/System Verilog is required.
• Basic to intermediate knowledge of JTAG/Boundary Scan (IEEE 1149.1) architecture and TAP controller operation.
• Hands-on experience with DFT methodologies is a plus and considered equivalent familiarity.
• Familiarity with JTAG-based post-silicon debug flows and bring-up strategies for SoC IO validation.
• Experience with boundary scan cell behavior and test access port (TAP) signal verification is a plus.
• Scripting experience or knowledge is a plus.
• Excellent analytical, communication (written and verbal), and documentation skills.

Benefits

The annual base salary range for this position, which could be performed in the US, is $91,000 - $232,000.* Range is dependent on numerous factors including job location, skills and experience. Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law. For more information on applicable equal employment regulations, please refer to the Know Your Rights: Workplace Discrimination is Illegal Poster.