Senior System and Manufacturing CoDesign Architect - Power, Thermal and Packaging

About the role

NVIDIA's Silicon Co-Design Group sits at the crossroads of architecture, silicon, systems, and manufacturing, where first principles thinking translates directly into product outcomes at scale. As GPU power density and thermal limits approach physical boundaries, the gap between system architecture needs and manufacturable, testable capabilities widens with every generation. This role exists to close that gap by identifying where physical constraints will erode NVIDIA's competitive edge before anyone else sees it coming, then building the cross-domain responses that ensure the next generation leapfrogs those limits entirely.

The problems here don't have known answers yet: every generation of NVIDIA silicon pushes closer to the limits of physics. The Co-Design Architect role isn't about optimizing within known bounds; it's about redrawing those bounds entirely. If you want your work to shape what's physically possible in the world's most demanding computing products, this is where that work happens.

What You'll Be Doing

• Power, Thermal & Packaging Limits Analysis: Gather and analyze the hard constraints of packaging, power delivery, and thermal dissipation against roadmap demands, predicting when those constraints will reduce competitiveness and acting before they do.
• Cross-Domain Solution Development: Develop solutions that span silicon features, packaging innovation, firmware and hardware co-design, and DFX updates, ensuring future products are not only performant but testable to the highest quality and reliability standards.
• Packaging Technology Evaluation: Assess emerging packaging technologies for their voltage/frequency, noise, reliability, and testability implications, determining which are worth adopting and the trade-offs each choice entails across the full system.
• System-Manufacturing Co-Design: Drive improvements in product performance, performance-per-watt, and provisioning efficiency through system-manufacturing co-design, with the scope to follow the work wherever the highest-impact opportunities lead, whether that's power, thermal, or adjacent domains.

Requirements

• BS/MS/PhD in EE, Physics, or CE (or equivalent experience)
• 12+ years relevant experience
• Deep understanding of power delivery, thermal dissipation, and current density in high-performance GPU/CPU systems
• Proven ability to convert physical-limit trends into impact, measures and solutions
• Demonstrated cross-functional influence across building, packaging, manufacturing, and test organizations

Ways To Stand Out From The Crowd

• Exceptional work ethic and up-leveling discussions to solve the real problems
• Native use of AI to accelerate build exploration and problem-space modeling
• Experience solving problems spanning electrical, thermal, mechanical, and manufacturing domains simultaneously

Pay

Base salary range: $196,000 – $310,500 USD for Level 5 and $232,000 – $368,000 USD for Level 6, determined by location, experience, and internal equity. Equity and benefits are also provided.