Senior Staff RTL Verification Engineer

About the Role

Impinj is a leading RAIN RFID provider and Internet of Things pioneer, inventing ways to connect everyday items to the Internet—including retail apparel, healthcare items, automobile parts, airline baggage, food, and more. With over 100 billion items connected to date and multiple Fortune 500 enterprises using our platform, we solve for a better understanding of our world.

The RAIN Reader IC (RIC) design group within Impinj Silicon Engineering is responsible for developing Impinj’s RIC products. The digital team owns the digital subsystems of these products, including the digital modem, microcontroller subsystem, digital control loops, calibration engines, and control/interface logic for analog IP. The team carries designs from architecture and micro-architecture definition through RTL, verification, DFT, timing closure, tapeout, post-silicon bring-up, and validation, partnering closely with chip architects, RF/analog designers, physical design, and CAD/EDA engineers.

Responsibilities

• Contribute to verification of Impinj’s next-generation RAIN RFID Reader ICs through all phases of product development.
• Define and develop state-of-the-art verification methodologies and infrastructure.
• Develop bus functional models, subsystem behavioral models, RTL code, and SystemVerilog testbenches.
• Write and execute directed and constrained-random tests to achieve comprehensive functional coverage.
• Define verification coverage metrics to evaluate and guarantee the tape-out of high-quality IC designs.
• Create SystemVerilog assertions, coverage monitors, and detailed test plans for features and functional blocks.
• Enhance verification efficiency by developing CI/CD workflows and custom toolkits for automation and reporting.
• Collaborate across logic, analog, test, and systems engineering teams to deliver new features and products to market.
• Support continuous improvement of existing RAIN RFID products through feature and performance enhancements.

Requirements

• Bachelor’s degree in Electrical or Computer Engineering, with 12 years of experience (or 8 years with an MS or 5 years with a PhD).
• 12+ years of experience in RTL verification.
• Experience in the verification of microcontroller microarchitectures and complex finite-state machines.
• Experience creating and implementing RTL functional verification test plans.
• Experience defining and developing bus functional models, subsystem behavioral models, and architectural checkers.
• Expertise in SystemVerilog and the Universal Verification Methodology (UVM).
• Hands-on experience developing SV assertions, reusable sequences, and coverage monitors.
• Proven ability to bring complex designs from concept through tapeout and production.
• Familiarity with CI/CD systems and RTL coverage tools.
• Scripting proficiency in Perl, Python, Ruby, or UNIX shell.
• Excellent written and verbal communication skills.

Benefits

• Competitive healthcare benefits and 401(k) plan with company match.
• Open paid time-off policy with respect for work/life balance.
• Eligibility for merit increases, annual bonus, and stock awards based on individual performance.
• Opportunity to earn sales incentives based on revenue or utilization (for eligible roles).
• Weekly Q&A sessions with the executive team.
• Support for remote work or a desk with a view at our Seattle headquarters (spectacular views of the Olympics, Lake Union, and Mt. Baker) or our Brazilian site in Porto Alegre.

Pay

The typical base pay range for this role across the US is $158,700 - $238,100. Individual base pay depends on factors such as complexity, responsibility, job duties, requirements, and relevant experience and skills.