Senior Staff Engineer, Digital IC Design

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow.

About the Role

The Custom Compute, Storage and Automotive Business Unit provides custom solutions for high performance compute, server, network processing, storage and Automotive applications. CCS&A products employ state-of-the-art custom and industry standard technologies such as CXL, PCIE, Ethernet, and ARM CPU cores.

Responsibilities

• Design, develop, implement, verify, and document micro-architecture and RTL for complex power management integrated circuits.
• Work closely with system and chip architects to design industrial quality implementations.
• Participate in the full design development cycle, end-to-end, from writing micro-architecture docs, RTL coding, specifications of timing, closely working with design verification teams to review test plans and execution of tests, ability to bring up block tests on silicon during lab testing, and maintenance of designed blocks and reusable IPs.
• Produce comprehensive block micro-architecture and register specs.
• Schedule detailed reviews with cross-functional teams.
• Evaluate and participate in improving design and verification methodologies.

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10+ years of related professional experience. Or Master’s/PhD in Computer Science, Electrical Engineering or related fields with 3-5+ years of experience.

Skills

• Strong background in SystemVerilog RTL coding techniques.
• Experience in high speed, multiple clock domain designs.
• Familiar with modern SoC architectures and various interface technologies such as AXI, DDR, Ethernet, PCIe.
• Experience in micro-architecture of complex custom/ASIC products involving Chip I/O, shared memory, and embedded processors.
• RTL design experience, synthesis, static-timing closure, formal verification, gate-level simulations, and block-level functional verification.
• Experience in implementation/timing closure for high speed design.
• Ability to create SVA assertions and apply formal verification concepts and tools.
• Ability to come up with creative and innovative solutions, and display technical leadership from within a team of engineers.
• Excellent verbal and written communication.
• Discipline and rigor in documentation.
• Ability to work efficiently and influentially with team members across multiple sites.
• Enthusiastic about exploring and applying new methods, tools, and process efficiency to ASIC design flow.
• Knowledge of scripting languages such as Python, Perl, Tcl, and UNIX shell is desirable.

Pay

Expected Base Pay Range (USD): $135,900 - $201,130 per annum. The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location, and market conditions.

Benefits

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include:

• Employee stock purchase plan with a 2-year look back.
• Family support programs to help balance work and home life.
• Robust mental health resources to prioritize emotional well-being.
• Recognition and service awards to celebrate contributions and milestones.