Senior Staff Engineer Digital IC Build Flow and Methodology

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

We are seeking a Senior Engineer to architect, implement, and maintain scalable build scripts and front-end methodology for complex digital IC designs. This role focuses on improving compilation, elaboration, simulation, and regression flow across block, subsystem, and full-chip designs, with an emphasis on performance, correctness, and developer productivity. The ideal candidate combines strong software engineering skills with deep understanding of ASIC/SoC design workflows and EDA tooling and enjoys owning end-to-end infrastructure used daily by large design and verification teams.

Key Responsibilities

• Design, implement, and maintain chip design build flows supporting block, subsystem, full-chip, and multi-chip simulations.
• Develop and own build scripts and orchestration logic for compile, elaborate, simulate, and regression workflows.
• Improve build performance through dependency analysis, incremental builds, caching, and flow optimization.
• Define and evolve methodology standards for front-end design and verification flows.
• Arcitect and enhance CI / pre-submit verification flows to improve quality and turnaround time.
• Integrate and support industry EDA tools within robust scripted flows.
• Collaborate with RTL, DV, methodology, and infrastructure teams.
• Debug complex infrastructure and build-system issues.
• Drive adoption through documentation and training.

What We're Looking For

• Bachelor’s or Master’s degrees in electrical engineering, Computer Engineering, Computer Science, or related field.
• 8+ years of experience in ASIC/SoC design, verification, or methodology roles.
• Strong programming skills in Python and at least one of TCL, C/C++, or shell scripting.
• Experience with make-based or graph-based build systems.
• Understanding of front-end chip design flows.
• Experience debugging large-scale infrastructure issues.
• Familiarity with EDA toolchains.
• Strong problem-solving and collaboration skills.

Preferred Qualifications

• Experience with next-generation or programmable build flows.
• CI systems such as Jenkins.
• Multi-chip or chiplet-based designs.
• Bazel or similar dependency-graph build systems.
• Compute-farm environments.
• Mentoring junior engineers.

Expected Base Pay Range (USD)

$151,000 - $223,440, $ per annum

Additional Compensation and Benefit Elements

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.