Senior Staff Analog Mixed-Signal Design Engineer

About the Role

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. As part of the Central Engineering organization, you’ll contribute to advanced analog IPs that drive Marvell’s high-speed wireline and optical products, making an outsized impact on both the organization and future technological innovation.

Responsibilities

• Design and develop high-speed and low-power analog mixed-signal circuits in advanced CMOS technologies, with a focus on SerDes (Serializer/Deserializer) die-to-die communication and high-speed wireline design.
• Design analog mixed-signal blocks such as: Clock Generation and Distribution, DLLs, custom high-speed digital circuits, CTLE, VGA, TX Drivers, ADCs, DACs, and Regulators.
• Supervise and guide layout activities to ensure design accuracy and performance.
• Conduct post-silicon testing and validation of analog mixed-signal circuits.
• Collaborate with cross-functional teams to ensure successful project execution.
• Utilize state-of-the-art EDA tools for design automation and verification.
• Prepare and maintain detailed documentation of design processes and results.
• Prepare and participate in design reviews to ensure design quality and compliance with project requirements.

Requirements

• MS/PhD in Electrical Engineering and 7+ years of demonstrated experience in analog mixed-signal design, specifically in one or more of the following areas: ADC, DAC, voltage regulators, clock generation and distribution circuits, DLLs, custom high-speed digital circuits, CTLE, VGA, and TX drivers.
• Expertise in high-speed and low-power design within advanced CMOS technologies, including knowledge of trade-offs and optimization techniques for performance and power efficiency.
• Ability to identify, analyze, and resolve complex design issues, ensuring robust and reliable circuit performance.
• Experience in overseeing layout engineers, providing guidance on best practices, and ensuring that layout designs meet performance, area, and reliability requirements.
• Experience in post-silicon validation, including hands-on experience with lab equipment, debugging, and characterization of analog mixed-signal circuits.
• Good understanding of CMOS process technology, device physics, and the impact of process variations on circuit performance.
• Proficient in using electronic design automation (EDA) tools for schematic capture, simulation, layout, and verification, such as Cadence, Synopsys, or Mentor Graphics.
• Strong communication, presentation, and documentation skills.

Pay

Expected base pay range: $147,830 – $221,400 per annum. The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location, and market conditions.

Benefits

Marvell provides comprehensive benefits supporting employees at every stage, including:

• Financial well-being: Employee stock purchase plan with a 2-year look back.
• Family support: Programs to help balance work and home life.
• Mental and physical health: Robust resources to prioritize emotional well-being.
• Recognition: Service awards to celebrate contributions and milestones.