Senior SoC Verification Methodology Engineer

About the role

We are looking for a Senior Verification Infrastructure Engineer to join the SoC verification team at NVIDIA. In this role, you will build, develop, and maintain scalable verification infrastructure that enables efficient system-level verification across System level Simulations, Emulation, FPGA prototyping, and C-model environments. Your work will be foundational to ensuring correctness, performance, and quality of NVIDIA’s SoCs used across AI Datacenters, self-driving cars, robotics, and embedded platforms. This is your chance to work with innovative technology and make a significant impact on the future of computing!

Responsibilities

• Build and develop testbench infrastructure and associated flows for full chip level verification of NVIDIA SoCs
• Develop, combine, and support Verification IP (VIP) and reusable verification components
• Develop and improve stimulus frameworks supporting: RTL simulation, Hardware emulation, FGPA prototyping, C-model and hybrid model verification
• Work closely with EDA vendors to co-develop and deploy new verification tooling
• Collaborate closely with design, architecture, performance, and software teams to align verification infrastructure with evolving product requirements
• Drive best practices in verification methodology, scalability, performance optimization, and debuggability
• Support bring-up and debug of system-level test environments and flows

Requirements

• Master’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience
• 8+ years in the following areas: SystemVerilog, UVM, and modern verification methodologies
• Experience working with testbenches, VIP, and reusable verification frameworks
• Hands-on experience with RTL simulation and at least one of the following: Hardware emulation, FGPA prototyping, C-model or virtual platform verification
• Strong scripting skills in Python or Perl, or similiar for automation and tooling
• Strong debugging skills across hardware and software boundaries

Qualifications

• Master’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience
• 8+ years in the following areas: SystemVerilog, UVM, and modern verification methodologies
• Experience working with testbenches, VIP, and reusable verification frameworks
• Hands-on experience with RTL simulation and at least one of the following: Hardware emulation, FGPA prototyping, C-model or virtual platform verification
• Strong scripting skills in Python or Perl, or similiar for automation and tooling
• Strong debugging skills across hardware and software boundaries

Skills

• SystemVerilog, UVM, and modern verification methodologies
• Testbenches, VIP, and reusable verification frameworks
• RTL simulation and at least one of the following: Hardware emulation, FGPA prototyping, C-model or virtual platform verification
• Python or Perl scripting for automation and tooling
• Debugging skills across hardware and software boundaries

Benefits

• Base salary range: $168,000 - $264,500 for Level 4, and $196,000 - $310,500 for Level 5
• Eligible for equity and benefits

Pay

• Base salary determined based on location, experience, and position comparison

Schedule

• Not specified

Benefits

• Not specified

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