Senior SoC Physical Layout & Full-Chip Integration Engineer

We need to output HTML fragment with sections: About the role, Responsibilities, Qualifications, Benefits, Pay, Schedule? Only include sections if posting has real specific content. Let's parse. Job Description includes "About The Role" paragraph. Then "What You'll Do" responsibilities list. Then "Why Join Intel Foundry?" maybe could be considered Benefits? But they have a Benefits section later: "Benefits We offer a total compensation package...". Also "Annual Salary Range..." gives pay. Work Model gives schedule? It says hybrid work model eligible. That's schedule info. So we can include Schedule section. We must not repeat job title. No Job ID. Remove boilerplate like EEO etc. Also remove "Posting Statement", "Position of Trust N/A", "ADDITIONAL INFORMATION". Also remove "Job Type Experienced Hire Shift Shift 1 (United States of America)" maybe not needed. We need to preserve all substantive info. We need headings:

for section headings: About the role, Responsibilities, Qualifications, Benefits, Pay, Schedule. Use

• for any list of duties/requirements/benefits. Use

  for prose. We must only include sections when posting has real specific content. All those have content. Let's extract content. About the role: paragraph from "About The Role Join the Design Technology Platform..." up to before "What You'll Do". Let's capture that paragraph. Responsibilities: bullet list under "What You'll Do Responsibilities include, but are not limited to:" then list items. Also later "Successful Candidates Will Demonstrate" maybe could be considered Qualifications? Actually that's more like desired traits; but Qualifications section already covers minimum/preferred qualifications. We could treat "Successful Candidates Will Demonstrate" as part of Qualifications? But we already have Qualifications section with minimum and preferred. We could include those traits under Qualifications as a list? However instructions: Use

  • for any list of duties/requirements/benefits. The "Successful Candidates Will Demonstrate" is a list of traits; could be considered requirements. But we already have Qualifications section with minimum and preferred. Might be okay to include them as part of Qualifications as a list under "Preferred Qualifications"? But they are not explicitly labeled as preferred. Safer to keep them under Qualifications as a list? However the posting already has a Qualifications section with minimum and preferred. We could incorporate the "Successful Candidates Will Demonstrate" as part of Qualifications (maybe as additional traits). But we must not invent content; we can keep them as a separate section like "Key Competencies"? But we only allowed headings from list: About the role, Responsibilities, Requirements, Qualifications, Skills, Benefits, Pay, Schedule. There's no "Key Competencies". Could put them under Qualifications as part of the list. Or under Skills? There's Skills heading allowed. Could treat them as Skills. But better to follow the posting: they have Minimum Qualifications and Preferred Qualifications. So we will output Qualifications section with two subparts? But we need to use
    • for any list. We could have a

      describing minimum qualifications, then a

      for list items. Similarly for preferred. Let's extract Minimum Qualifications: - Masters' degree in Electrical Engineering, Computer Engineering, or a related field with 4+ years of industry experience. OR a PhD’s degree in the same field with 1+ years of industry experience. - Your Experience Outlined Above Must Be In The Following: - Custom/analog/mixed-signal layout design experience in advanced technology nodes. - Front-end (FEOL) layout design rules, transistor-level matching, parasitic layout concepts, and custom silicon structures. - Debugging skills in physical verification (LVS, DRC, and DFM) using industry-standard verification engines (such as Calibre or ICV), with a proven ability to solve complex, systemic layout errors. - Tcl, Python, or SKILL to automate layout creation, checking, and full-chip database manipulation. Preferred Qualifications: - Experience with top-level floorplanning, RDL/bump planning, or backside power delivery (PowerVia) implementation. - Proven track record of collaborating with PDK and Technology Development teams on design rule definitions, test structure vehicles, or DRC suppression strategies. - Experience managing physical tapeout schedules, IP tracking matrices, and formal physical design Quality Assurance (QA) flows. - Familiarity with custom layout environments (such as Cadence Virtuoso) and translating custom databases into full-chip NDM flows. - Previous related work experience in a semiconductor foundry preferred. Also location info: Primary – Hillsboro OR Additional – Chandler AZ, Austin TX. Also Job Type Experienced Hire Shift Shift 1 (United States of America). Primary Location: US, Oregon, Hillsboro Additional Locations: US, Arizona, Phoenix, US, Texas, Austin. Might be considered Schedule? Not exactly. Schedule is about work model hybrid. We'll include Schedule section with hybrid work model. Pay: Annual Salary Range: $122,440.00 - 232,190.00 USD. Benefits: paragraph about total compensation package, competitive pay, stock bonuses, benefit programs health, retirement, vacation. Also "See Intel Benefits for more details." We should not include boilerplate like "See Intel Benefits for more details." maybe keep as part of Benefits paragraph. Now construct HTML. We'll have:

      About the role

      Join the Design Technology Platform (DTP) organization within Intel Foundry and help drive the development of the methodologies, physical layouts, and silicon platforms that enable next-generation semiconductor technologies. As a member of the X-Chip Full-Chip Integration team, you will play a key role in developing custom layout methodologies, leading full-chip physical integration, and driving physical verification and tapeout execution for advanced testchip and silicon lead vehicles on cutting-edge process technologies. This role is ideal for engineers who have a passion for custom layout design, advanced-node physical design methodologies, and solving complex physical integration challenges. You will work at the intersection of technology development, physical design, verification, and manufacturing, collaborating with experts across Intel Foundry to enable future process technologies and silicon solutions.

      Responsibilities

      • Lead full-chip floorplanning, physical integration, and tapeout activities for advanced-node silicon development vehicles.
      • Develop and enhance custom layout methodologies and physical design flows.
      • Drive physical verification closure, including DRC, LVS, DFM, density, and antenna rule compliance.
      • Collaborate with Technology Development, PDK, and EDA teams to implement scalable and manufacturable design solutions.
      • Analyze advanced-node design rules and contribute to design enablement for emerging process technologies, including FinFET and Gate-All-Around (GAA) architectures.
      • Develop automation solutions using Tcl, Python, SKILL, or similar scripting languages to improve design productivity and quality.
      • Coordinate cross-functional activities to ensure tape-in readiness, database integrity, and successful project execution.
      Maybe also include the "Successful Candidates Will Demonstrate" list? Could be under Skills or Qualifications. Since we have Qualifications section, we could add those as a list under Qualifications as "Key competencies". But better to follow the posting: they have Minimum and Preferred Qualifications. We'll put those under Qualifications. Thus Qualifications section:

      Qualifications

      Minimum Qualifications

      • Masters' degree in Electrical Engineering, Computer Engineering, or a related field with 4+ years of industry experience. OR a PhD’s degree in the same field with 1+ years of industry experience.
      • Custom/analog/mixed-signal layout design experience in advanced technology nodes.
      • Front-end (FEOL) layout design rules, transistor-level matching, parasitic layout concepts, and custom silicon structures.
      • Debugging skills in physical verification (LVS, DRC, and DFM) using industry-standard verification engines (such as Calibre or ICV), with a proven ability to solve complex, systemic layout errors.
      • Tcl, Python, or SKILL to automate layout creation, checking, and full-chip database manipulation.

      Preferred Qualifications

      • Experience with top-level floorplanning, RDL/bump planning, or backside power delivery (PowerVia) implementation.
      • Proven track record of collaborating with PDK and Technology Development teams on design rule definitions, test structure vehicles, or DRC suppression strategies.
      • Experience managing physical tapeout schedules, IP tracking matrices, and formal physical design Quality Assurance (QA) flows.
      • Familiarity with custom layout environments (such as Cadence Virtuoso) and translating custom databases into full-chip NDM flows.
      • Previous related work experience in a semiconductor foundry preferred.
      But we used inside

      . That's okay; still HTML fragment. Now Benefits:

      Benefits

      We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

      Pay:

      Pay

      Annual Salary Range for jobs which could be performed in the US: $122,440.00 - 232,190.00 USD. The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

      Schedule:

      Schedule

      This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

      We might also include location info? Not required as heading; could be placed in a paragraph under About the role or maybe separate? The instruction: do not put Job ID / requisition numbers as headings — fold minor metadata into a short

      or drop it. Location is minor metadata; we could add a short

      after About the role or maybe after Qualifications. But we already have sections; we could add a

      under About the role that includes location? But About the role already has a paragraph; we could append location info there. However we must preserve ALL substantive information; location is substantive. So we need to include it somewhere. Could add a separate short

      after About the role before Responsibilities, maybe under a heading? There's no heading for location; we can just add a

      with location details. Similarly, Job Type Experienced Hire Shift Shift 1 (United States of America) maybe minor; we could drop or fold into a short

      . Probably drop as not essential. Thus after About the role paragraph, add a

      with location: Primary – Hillsboro OR Additional – Chandler AZ, Austin TX. Also note Primary Location: US, Oregon, Hillsboro Additional Locations: US, Arizona, Phoenix, US, Texas, Austin. Might be redundant; we can combine. Let's craft:

      Primary location: Hillsboro, OR. Additional locations: Chandler, AZ; Austin, TX (also listed as Phoenix, AZ and Austin, TX in some fields).

      But we need to be accurate: The posting says: Location: Primary – Hillsboro OR Additional – Chandler AZ, Austin TX. Job Type Experienced Hire Shift Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: US, Arizona, Phoenix, US, Texas, Austin. So we can say: Primary location: Hillsboro