Senior R&D Engineer-17637

We Are You

You are a passionate software engineer with an electrical engineering background. You have a strong foundation in electrical circuits, VLSI design, semiconductor physics, or related areas. Proficient in C++ programming and designing efficient algorithms, you are comfortable moving between electromagnetic theory and production C++ code. You can work on a quasi-static model one day and optimize a data structure handling billions of elements the next day without compromising accuracy.

What You'll Be Doing

• Research, design, and implement new transistor level extraction capabilities for StarRC, focusing on modeling accuracy for FinFET and gate-all-around devices at 3nm, 2nm, and beyond.
• Develop parasitic models for interconnect capacitance, inductance, and resistance using pattern-matching techniques and field solver methods.
• Design efficient algorithms and data structures in C++ that handle massive layout datasets while maintaining extraction accuracy and runtime performance.
• Apply computational electromagnetics principles to solve complex extraction problems for advanced process nodes.
• Collaborate with engineers across layout, simulation, timing, and physical verification teams to ensure StarRC integrates seamlessly into customer signoff flows.
• Work directly with foundries and customers to resolve extraction challenges in CPU designs, 3D IC systems, and advanced packaging structures.

The Impact You Will Have

• Enable accurate signoff for chips at the most advanced process nodes, directly affecting whether billion-dollar designs can tape out on schedule.
• Improve extraction runtime and capacity so customers can close timing on larger, more complex SoCs without sacrificing accuracy.
• Deliver capabilities that help foundries and design teams understand parasitic effects in new process technologies before they become yield problems.
• Strengthen StarRC's position as the gold standard extraction tool by solving problems competitors cannot.
• Help customers across CPU, AI accelerator, and memory design teams achieve first-pass silicon success by catching parasitic issues early.
• Shape the technical direction of extraction technology through direct collaboration with leading foundries and design houses.

What You'll Need

• MS or PhD in Electrical Engineering, Computer Science, or Computer Engineering with 1+ years of relevant EDA software development experience.
• Proficiency in C++ programming, algorithm design, and data structures for large scale software systems.
• A strong background in computational electromagnetics, including experience with full-wave or quasi-static EM modeling, Maxwell's equations, and numerical methods such as FEM, BEM, or MoM.
• Understanding how parasitic effects impact circuit performance and signoff, experience with LVS, extraction, or circuit simulation flows is a plus.
• Familiarity with field solver technology or transmission line analysis is a plus.

The Team You'll Be Part Of

You will be a member of a high performing R&D team contributing to the development of StarRC, the EDA industry's gold standard for parasitic extraction. The team works on modeling physical effects for advanced process technologies, including FinFET at 7nm, 5nm, 3nm, 2nm, and beyond. You will collaborate closely with other product developers across layout design, simulations, timing, reliability verification, and physical verification.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process.