Senior Product Manager, Hardware (NPU IP)

Responsibilities

• Translate customer requirements, competitive pressure, and architectural constraints into a track-by-track feature list with explicit gating — what ships, what slips, what gets cut.
• Build the case for contested architecture decisions (e.g., dedicated requant unit vs. wider MAC array), run the tradeoff with the architects, and bring a recommendation to the PSC.
• Customer engagement. Named hardware product owner for anchor accounts. Present new features, ingest formal architecture feedback, and convert it into roadmap input.
• IP usability. Find what customers are silently working around — API wrappers, glue logic, custom RTL hooks, workaround scripts.
• Hardware competitive intelligence. Track Synopsys NPX6, Arm Ethos-U85, Ceva NeuPro-M, VeriSilicon Vivante, and NVIDIA Jetson at the architectural level. Translate competitor moves into specific feature requirements before gaps appear in customer evals.
• SoC integration positioning. Decide which integration knobs (AXI4/ACE-Lite, CoreSight, power-domain partitioning, performance counters) are exposed, which are productized, and how they're described in the integration guide.
• Functional safety positioning. Sequence FMEDA work, lockstep configurations, and safety-island architecture.

Requirements

• 5-8 years of PM experience on hardware or silicon products.
• Senior IC background.
• Customer-facing track record - You have run architecture reviews with sophisticated technical buyers — Tier 1 automotive, OEM SoC teams.
• IP-licensing rhythm - Customers integrate our IP for 18-24 months before silicon ships. Decisions today appear in production volume in 2028.
• Agent-pilled -You use agentic AI tools daily (Claude Code, Cursor, or equivalent) to produce work.
• Customer first
• Direct experience with at least two of: NPU/AI accelerator architecture, SoC integration, DSP/vector compute, automotive silicon, semiconductor IP licensing
• EE/CE/CS engineering degree or equivalent depth
• Experience with in-person technical customer reviews
• Preferred: RTL or silicon-implementation background — shipped a block, sat through tape-out, or owned a microarchitecture spec end-to-end
• Prior IP vendor experience (Synopsys, Arm, Ceva, Cadence, Imagination, VeriSilicon, Rambus, or similar)
• Direct exposure to the AI/ML compute stack at the architecture level — dataflow, quantization, sparsity, mixed-precision tradeoffs
• Japanese-market customer experience — our largest account and a meaningful share of the pipeline is in Japan

Benefits

• Competitive salary and meaningful equity
• Medical, dental, and vision plan options starting on day one
• 401(k) retirement plan
• Flexible paid time off (unlimited, non-accrual)
• Company-provided lunches and a stocked kitchen
• Downtown Burlingame office, walking distance from Caltrain

Skills and growth

• Initiative
• Collaboration
• Completion