Senior Principal ASIC FPGA Engineer

Basic Qualifications

• Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 10 years of relevant experience; or Master's degree plus a minimum of 8 years of relevant experience
• Department of Defense Secret security clearance is required at time of hire
• Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information
• U.S. citizenship is required

Responsibilities

• Own the architecture — Define the ASIC/FPGA technical approach from concept through silicon, including system partitioning, microarchitecture, and interface definition
• Drive RTL design — Lead detailed RTL development with a focus on correctness: bus fabric integrity, clock domain crossings, reset order-of-operations, and design-for-verification
• Close timing — Navigate synthesis, place and route, and static timing analysis with deep understanding of what it takes to meet timing in advanced process nodes — not just run the tools, but fix the problems
• Lead verification — Serve as the primary point of contact for verification activities; develop and own test and simulation plans that establish rigorous functional criteria; verify results and drive closure on failures
• Triage and track — Own JIRA triage for the team: reviewing incoming issues, prioritizing work items, and ensuring the backlog reflects program reality
• Lead code reviews — Conduct and lead RTL code reviews, setting the technical bar and providing actionable, constructive feedback to engineers at all levels
• Support program planning — Contribute to Integrated Master Schedule (IMS) development and Earned Value (EV) reporting; provide accurate technical input on task status, completion criteria, and schedule risk
• Evaluate process flows — High-level design through GDSII, including synthesis, P&R, timing, power analysis, and DFT considerations
• Guide technology selection — Assess foundry technologies, device libraries, IP cores, and EDA tooling to inform design decisions
• Support proposals and subcontracts — Lead ASIC/FPGA technical approach on large proposals; may serve as book boss on medium proposals; manage technical subcontracts including SOW development, source selection, and work product acceptance
• Grow the team — Mentor junior and mid-level engineers; contribute to the development and improvement of organizational ASIC/FPGA design processes
• Collaborate broadly — Participate in multi-divisional or multi-company Integrated Product Teams and working groups

Experience

• 10–15+ years of ASIC/FPGA design experience, with the majority spent as an RTL designer — not in a purely backend or physical design role
• Proven experience taking designs through full ASIC tape-out, including timing closure, physical verification, and post-silicon bring-up
• Deep familiarity with FinFET process nodes (7nm, 5nm, or similar) — understanding the nuances of FinFET vs. planar technology is a meaningful differentiator for this role
• Experience with commercial foundry flows (TSMC, GlobalFoundries, Samsung, or equivalent)
• Demonstrated expertise in:
  • RTL design and microarchitecture definition
  • Bus fabric design and correctness verification
  • Clock domain crossing (CDC) analysis and closure
  • Reset sequencing and order-of-operations validation
  • Timing closure at advanced nodes — not just constraint writing, but root cause analysis and fixing
  • Power analysis and optimization

Skills & Knowledge

• Expert-level understanding of ASIC/FPGA engineering concepts, RTL coding practices, and synthesis flows
• Strong familiarity with industry-standard EDA tools (synthesis, simulation, formal verification, STA)
• Demonstrated ability to operate independently — identifying problems, driving resolution, and keeping work moving without requiring day-to-day direction
• Ability to evaluate vendor and foundry capabilities to support product development decisions
• Track record of innovative technical contributions — not just executing to spec, but shaping the approach
• Solid understanding of organizational processes and the ability to apply them pragmatically across a program lifecycle, including schedule management and earned value inputs
• Proficiency in JIRA for issue tracking and backlog management
• Proficiency in Microsoft Office for documentation and communication

Pay

Target salary range: USD $191,146.00/Yr. - USD $212,053.00/Yr. This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary.