Senior Power Integrity Engineer - LPU Packaging

About the role

NVIDIA is seeking a Senior Power Integrity Engineer to join our LPU Packaging team. This role involves defining best-in-class power delivery design and optimization practices, owning PI specifications and methodologies, driving system-level PI design, and validating designs through lab measurements.

Responsibilities

• Define best-in-class power delivery design and optimization practices from die/package through board, tray, and rack levels for the full product development cycle
• Own the PI specification and methodology for assigned products, defining PDN targets including impedance, droop, noise, and transient response for GPU, HBM, and high-speed SerDes
• Architect package-level PDNs by collaborating with design teams on bump/ball maps, via structures, and decoupling strategies for FCBGA and 25D/3D integrations
• Drive system-level PI design, including board-level PDN planning, decap placement, and VRM interfaces while co-optimizing with SI, thermal, and mechanical teams
• Perform PI extraction and simulation for advanced packages and develop integrated chip-package-board co-simulation flows using industry-standard tools
• Generate and deploy reusable PI models, such as SPICE, S-parameter, and IBIS-AMI, for use by internal and external partners
• Define and execute comprehensive lab validation plans to correlate measured impedance, noise, and droop against simulation data and specifications
• Debug complex system-level issues including rail noise, jitter-induced errors, resets, and margin loss during hardware testing and validation

Requirements

• MS or PhD in Electrical Engineering or a related field, or equivalent experience
• 12+ years of relevant work experience in Power Integrity
• A strong background in power integrity for high-current, low-voltage rails within large GPUs, ASICs, or CPUs
• Proven ownership of the chip-package-board PDN design and sign-off process
• Hands-on experience with FCBGA, 25D/3D integration, HBM, or similar high-power, high-pin-count packages
• Direct experience in the co-design of bump/ball maps, power/ground planes, and decoupling capacitor networks
• Proficiency with frequency-domain PDN impedance analysis and time-domain transient/droop simulation tools (eg, PowerSI, PowerDC, Sigrity, RedHawk, Totem, HFSS, SIwave, ADS, or SPICE)
• A deep understanding of board-level PDN design, including stack-up definition, plane partitioning, and VRM placement on high-layer-count accelerator boards
• Experience in executing lab measurements using VNAs, oscilloscopes, and PDN analyzers to correlate measured noise and droop to original specifications

Qualifications

• Demonstrated leadership of end-to-end PI for a major GPU, CPU, or ASIC program from initial concept through mass production
• Experience with data center or cloud hardware, specifically regarding rack-level power distribution and how PI choices impact performance headroom
• Strong communication skills with the ability to clearly explain complex PDN trade-offs and risks to both technical teams and program stakeholders

Skills

• Data center or cloud hardware experience
• Co-design of SI and PI for high-speed interfaces like PCIe, NVLink, CXL, or Ethernet SerDes to mitigate jitter and noise coupling

Benefits

• Highest competitive salaries
• Comprehensive benefits package

Pay

• Base salary range: $196,000 - $310,500 for Level 5, and $232,000 - $368,000 for Level 6

Schedule

• Full-time position