Senior Physical Design Engineer - Neuromorphic Computing

About the Role

For nearly a decade, Intel's Neuromorphic Computing Lab—together with a global ecosystem of 250+ research groups—has explored architectures, algorithms, and software inspired by the brain's extraordinary efficiency, scalability, and adaptability. Our Loihi series of research chips pioneered event-driven, sparse, and massively parallel neuro-inspired processing, fueling over 100 peer-reviewed publications that validate the promise of this novel approach. Now, we're entering an exciting new chapter: transforming these breakthroughs into real-world products that will power the coming era of physical AI systems—beyond the reach of GPUs and mainstream AI accelerators.

We are seeking a senior physical design engineer who is passionate about driving innovation at the intersection of advanced semiconductor technologies, physical AI, and next-generation computing architectures. As a member of Intel's neuromorphic silicon team, you will engineer physical integration solutions spanning chiplet and advanced packaging technologies. In this hands-on role, you will help overcome the performance, area, and power limitations of today's AI architectures. You will also lead block- and chip-level closure activities, driving designs to achieve their performance, power, and area targets. An openness to learning new technologies and methodologies, such as asynchronous design techniques and AI-driven automation and debug, is essential.

Responsibilities

• Understand system specification to drive down package and die-level requirements.
• Architect full-chip floorplans and work with designers to set up partition-level floorplans with macro/pin placements and keep-outs.
• Work with RTL designers to define timing constraints; run synthesis and place-and-route trials; fix timing, EM/IR, LVS, and DRC violations.
• Run back-annotated VCS+SDF simulations and iterate on meeting power/performance targets by providing feedback to designers.
• Write custom scripts and define tool flows to manipulate synthesis and physical design tools for low power/high performance custom designs.

Requirements

• Bachelor's and 6+ years OR Master's and 4+ years of hands-on physical design experience, delivering multiple silicon tape-outs.
• 6+ years of experience in setting up floorplans, defining timing and power constraints, and iterating through synthesis, place, and route to meet product KPIs.
• 6+ years of experience with scripting languages such as Perl, TCL, Python, etc.
• 4+ years of experience in debugging FEV and RV reports and planning ECOs.
• 2+ years of experience in chiplet integration and/or advanced packaging.
• 1+ year of experience using AI tools for setting up tool flows, debugging, and improving overall productivity.

Preferred Qualifications

• Static timing experience with multiple interfaces (SerDes, UCIe, etc.).
• Experience in both Cadence (Virtuoso) and Synopsys (Fusion Compiler, Primetime, StarRC, SiliconSmart, VCS) tools.
• Experience in EDA/CAD software development using object-oriented programming languages like Java or C++.
• Experience in asynchronous architectures and circuits.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

Pay

Annual Salary Range for jobs which could be performed in the US: $164,470.00 - $269,100.00 USD. The range displayed reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.

Schedule

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.