Physical Design Engineer - Neuromorphic Computing

About the Role

The world is transforming—and so is Intel. We are a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams continually search for tomorrow's technology.

For nearly a decade, Intel's Neuromorphic Computing Lab—together with a global ecosystem of 250+ research groups—has explored architectures, algorithms, and software inspired by the brain's extraordinary efficiency, scalability, and adaptability. Our Loihi series of research chips pioneered event-driven, sparse, and massively parallel neuro-inspired processing, fueling over 100 peer-reviewed publications. Now, we're entering an exciting new chapter: transforming these breakthroughs into real-world products that will power the coming era of physical AI systems—beyond the reach of GPUs and mainstream AI accelerators.

If you are passionate about pushing the boundaries of computing, from transistor-level innovation to software abstractions, join us. Help define the next wave of AI technology that harnesses the proven advantages of Intel's neuromorphic computing technology with the versatility demanded by modern AI workloads.

Responsibilities

• Understand design dataflow and chip-level floor-planning constraints to set up partition floorplans with macro/pin placements and keep-outs.
• Work with RTL designers to define timing constraints; run synthesis and place-and-route trials; fix timing, EM/IR, and DRC violations.
• Run back-annotated VCS+SDF simulations and iterate on meeting power/performance targets.
• Write custom scripts and define tool flows to manipulate synthesis and physical design tools for low power/high performance custom designs.

Qualifications

Minimum Qualifications

• Bachelor’s degree with 4+ years, Master’s degree with 3+ years, or PhD with hands-on physical design experience.
• 3+ years of experience in synthesis, place and route, and timing/layout closure.
• 3+ years of experience with scripting languages such as Perl, TCL, or Python.

Preferred Qualifications

• Experience in chiplet integration and/or advanced packaging.
• Static timing experience with multiple interfaces (SerDes, UCIe, etc.).
• Experience in Synopsys tools (Fusion Compiler, Primetime, VCS).
• Experience in EDA/CAD software development using object-oriented programming languages like Java or C++.
• Experience in asynchronous architectures and circuits.

Locations

US, Oregon, Hillsboro; US, California, Folsom; US, California, San Jose; US, California, Santa Clara

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

Pay

Annual Salary Range for jobs which could be performed in the US: $122,440.00 - $232,190.00 USD. The range reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.

Schedule

This role is eligible for our hybrid work model, which allows employees to split their time between working on-site at their assigned Intel site and off-site.