Senior Package Design Engineer – Semiconductor Packaging

About the role

We're seeking an experienced Package Design Engineer to support early-stage semiconductor package development through package-board co-design activities. You'll develop routing studies, board design mockups, and electrical modeling collateral used to optimize package architecture, BGA implementation, and overall system performance.

What you will be doing

• Create PCB routing studies supporting package development
• Develop board-level design mockups for electrical modeling
• Perform package escape routing and BGA optimization studies
• Analyze routing congestion and layer utilization
• Support Signal Integrity and Power Integrity modeling
• Build representative PCB environments for package evaluation
• Collaborate with package, SI/PI, mechanical, and systems engineering teams
• Evaluate design tradeoffs during early architecture phases
• Contribute automation and workflow improvement initiatives
• Support advanced package-board co-design activities

Must have skills

• 3+ years using Cadence Allegro PCB Designer
• Experience with high-pin-count BGA layouts
• Strong PCB routing expertise
• Understanding of package escape strategies
• Knowledge of Signal Integrity fundamentals
• Knowledge of Power Integrity fundamentals
• Experience with complex, high-speed interconnects
• Strong cross-functional communication skills
• Comfortable working through ambiguous engineering challenges
• Interest in AI-driven engineering automation

Why join us

• Work on some of the industry's most advanced AI semiconductor programs
• Collaborate directly with world-class silicon, package, SI/PI, and systems engineers
• Gain exposure to emerging packaging technologies including chiplets and 2.5D integration
• Influence package architecture during early design phases rather than production support
• Join a rapidly growing engineering organization tackling next-generation computing challenges

Location: Santa Clara, CA • Hybrid • Minimal travel