Senior Mixed Signal Design Engineer

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can take on, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence.

About the role

This is a diverse team working with innovative, ground-breaking technology. If you are someone that loves a challenge, come join this complementary team and help move the needle! As a member of our Mixed Signal team, you will lead the design of CMOS high-speed interface circuits and mixed-signal circuits, with strong hands-on experience in the lab for silicon validation, debugging, characterization, and bring-up.

Responsibilities

• Lead design and implementation of high-speed interface circuits
• Design projects include high-speed transceivers and high-frequency PLLs
• Design, simulation, and verification of mixed-signal circuits
• Supervise IC circuit/mask designers, provide floorplan and layout guidelines
• Support lab characterization of silicon
• Tackle challenges of circuit design in deep submicron CMOS
• Take designs through implementation and productization
• Work with multi-functional teams

Requirements

• MS in Electrical Engineering or equivalent experience
• 4+ years of design experience in CMOS analog/mixed-signal circuit design
• Solid understanding of Cadence custom design tools, circuit simulator, and timing analysis tools
• Proven experience in crafting and mentoring designers
• Extensive experience in Tx, Rx, CDR, and PLL for high-speed IO interfaces
• In-depth understanding of deep submicron CMOS process and related circuit design issues
• Experience in silicon bring-up, debugging, and use of lab instrumentation

Preferred Qualifications

• Knowledge in system-level timing budget, signal integrity, and power integrity
• Experience in Verilog, Matlab, Primetime, or Nanotime

Pay

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 196,000 USD - 310,500 USD for Level 5, and 232,000 USD - 368,000 USD for Level 6. You will also be eligible for equity and benefits.