Senior Memory Controller Verification Engineer

About the role

NVIDIA is seeking a Senior Verification Engineer for their GPU Memory Subsystem IP verification team. The ideal candidate will partner with design and architecture teams to ensure the right implementation choices are made, develop verification infrastructure, and ensure code and functional coverage.

Responsibilities

• Develop verification infrastructure (testbenches, BFMs, checkers, monitors, randoms)
• Come up with, review, and drive test plan execution for planned features
• Understand the performance requirements of your IP, come up with, review, and drive performance test plan for your IP
• Ensure code and functional coverage of all the RTL which you will verify
• Work with and enable FPGA and software teams to ensure that software is tested
• Plan for and be involved with post-silicon verification and debug

Requirements

• BS / MS or equivalent experience with 6+ years of ASIC verification experience of complex design units
• Good attention to detail, teamwork, problem-solving skills, and success in previous roles
• Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB)
• Background with System Verilog and UVM based methodology for ASIC verification

Qualifications

• Strong C/C++ programming experience
• Prior Design or Verification experience of dynamic memory controllers (ddr{2, 3, 4, 5}, lpddr{2, 3,4,5,6}, HBM, or GDDR)
• Strong debugging and problem-solving skills
• Scripting knowledge (Python/Perl/shell)
• Good interpersonal skills and ability & desire to work as a part of a team

Skills

• Experience with System Verilog and UVM
• Experience with ASIC verification tools
• Experience with dynamic memory controllers
• Experience with scripting languages

Benefits

• Competitive salaries
• Generous benefits package
• Equity options

Pay

• Base salary range: $168,000 - $264,500 for Level 4, and $196,000 - $310,500 for Level 5

Schedule

• Full-time